SystemVerilog and Verilog X Optimism – What About X Pessimism?
In my previous post about SystemVerilog and Verilog X Optimism – You May Not Be Simulating What You Think, I discussed what is Verilog X optimism, and some coding styles that are prone to Verilog X optimism bugs. So how do you avoid potential bugs that Verilog X optimism can introduce? One technique that has … Read more