A list of all posts in the Verilog category
Verilog
- Verilog Module for Design and Testbench
- Verilog Always Block for RTL Modeling
- Verilog Generate Configurable RTL Designs
- Verilog Arrays Plain and Simple
- Verilog reg, Verilog wire, SystemVerilog logic. What’s the difference?
- Verilog twins: case, casez, casex. Which Should I Use?
- SystemVerilog and Verilog X Optimism – Hardware-like X Propagation with Xprop
- SystemVerilog and Verilog X Optimism – What About X Pessimism?
- SystemVerilog and Verilog X Optimism – You May Not Be Simulating What You Think