CDC toggle to pulse generator (destination clock) wave
SoC Design Engineer at Intel Corporation
Jason has 14 years' experience in the semiconductor industry, designing and verifying Solid State Drive controller SoC. His areas of workinclude microarchitecture and RTL design, dynamic and formal verification using UVM and Cadence JasperGold, and full-chip low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in any way.
Latest posts by Jason Yu (see all)
- How Chiplets Assemble Into the Most Advanced SoCs - September 28, 2022
- Verilog Module for Design and Testbench - June 19, 2022
- Verilog Always Block for RTL Modeling - April 13, 2022