How Chiplets Assemble Into the Most Advanced SoCs

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Chiplet based SoC designs have become mainstream in high end SoCs. This article explores technologies used to build chiplet designs.

Verilog Module for Design and Testbench

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A Verilog module is a building block that defines a design or testbench component, by defining the building block’s ports and internal behaviour. Higher-level modules can embed lower-level modules to create hierarchical designs. Different Verilog modules communicate with each other through Verilog port. Together, the many Verilog modules communicate and model dataflow of a larger, … Read more

Verilog Always Block for RTL Modeling

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Verilog always block is a procedural statement that starts an activity flow. It is essentially an infinite loop. However, when combined with a Verilog event expression, it can be used to model combinational and sequential logic.

Verilog Generate Configurable RTL Designs

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Verilog generate statement is a powerful construct for writing configurable, synthesizable RTL. It can be used to create multiple instantiations of modules and code, or conditionally instantiate blocks of code. However, many Verilog programmers often have questions about how to use Verilog generate effectively. In this article, I will review the usage of three forms … Read more

SystemVerilog Arrays, Flexible and Synthesizable

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In my last article on plain old Verilog Arrays, I discussed their very limited feature set. In comparison, SystemVerilog arrays have greatly expanded capabilities both for writing synthesizable RTL, and for writing non-synthesizable test benches. In this article, we’ll take a look at the synthesizable features of SystemVerilog Arrays we can use when writing design … Read more

Verilog Arrays Plain and Simple

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Arrays are an integral part of many modern programming languages. Verilog arrays are quite simple; the Verilog-2005 standard has only 2 pages describing arrays, a stark contrast from SystemVerilog-2012 which has 20+ pages on arrays. Having a good understanding of what array features are available in plain Verilog will help understand the motivation and improvements … Read more

Verilog reg, Verilog wire, SystemVerilog logic. What’s the difference?

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The difference between Verilog reg and Verilog wire frequently confuses many programmers just starting with the language (certainly confused me!). As a beginner, I was told to follow these guidelines, which seemed to generally work: Use Verilog reg for left hand side (LHS) of signals assigned inside in always blocks Use Verilog wire for LHS … Read more

SystemVerilog Struct and Union – for Designers too

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SystemVerilog struct (ure) and union are very similar to their C programming counterparts, so you may already have a good idea of how they work. But have you tried using them in your RTL design? When used effectively, they can simplify your code and save a lot of typing. Recently, I tried incorporating SystemVerilog struct … Read more

Clock Domain Crossing Design – Part 3

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In Clock Domain Crossing (CDC) Design – Part 2, I discussed potential problems with passing multiple signals across a clock domain, and one effective and safe way to do so. That circuit, however, does hot handle the case when the destination side logic cannot accept data and needs to back-pressure the source side. The two … Read more

Clock Domain Crossing Design – Part 2

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In Clock Domain Crossing (CDC) Techniques – Part 1, I briefly discussed metastability and two methods to safely synchronize a single bit. While those techniques are commonly used, in many applications we need to synchronize multiple control or data bits, like an encoded state or a data bus. Synchronizing multiple bits brings a host of … Read more