Arrays are an integral part of many modern programming languages. Verilog arrays are quite simple; the Verilog-2005 standard has only 2 pages describing arrays, a stark contrast from SystemVerilog-2012 which has 20+ pages on arrays. Having a good understanding of what array features are available in plain Verilog will help understand the motivation and improvements introduced in SystemVerilog. In this article I will restrict the discussion to plain Verilog arrays, and discuss SystemVerilog arrays in an upcoming post.
Verilog Arrays
Verilog arrays can be used to group elements into multidimensional objects to be manipulated more easily. Since Verilog does not have user-defined types, we are restricted to arrays of built-in Verilog types like nets, regs, and other Verilog variable types.
Each array dimension is declared by having the min and max indices in square brackets. Array indices can be written in either direction:
array_name[least_significant_index:most_significant_index], e.g. array1[0:7]
array_name[most_significant_index:least_significant_index], e.g. array2[7:0]
Personally I prefer the array2 form for consistency, since I also write vector indices (square brackets before the array name) in [most_significant:least_significant] form. However, this is only a preference not a requirement.
A multi-dimensional array can be declared by having multiple dimensions after the array declaration. Any square brackets before the array identifier is part of the data type that is being replicated in the array.
The Verilog-2005 specification also calls a one-dimensional array with elements of type reg a memory. It is useful for modeling memory elements like read-only memory (ROM), and random access memory (RAM).
Verilog arrays are synthesizable, so you can use them in synthesizable RTL code.
reg [31:0] x[127:0]; // 128-element array of 32-bit wide reg
wire[15:0] y[ 7:0], z[7:0]; // 2 arrays of 16-bit wide wires indexed from 7 to 0
reg [ 7:0] mema [255:0]; // 256-entry memory mema of 8-bit registers
reg arrayb [ 7:0][255:0]; // two-dimensional array of one bit registers
Assigning and Copying Verilog Arrays
Verilog arrays can only be referenced one element at a time. Therefore, an array has to be copied a single element at a time. Array initialization has to happen a single element at a time. It is possible, however, to loop through array elements with a generate or similar loop construct. Elements of a memory must also be referenced one element at a time.
initial begin mema = 0; // Illegal syntax - Attempt to write to entire array arrayb[1] = 0; // Illegal syntax - Attempt to write to elements [1][255]...[1][0] arrayb[1][31:12] = 0; // Illegal syntax - Attempt to write to multiple elements mema[1] = 0; // Assigns 0 to the second element of mema arrayb[1][0] = 0; // Assigns 0 to the bit referenced by indices [1][0] end // Generate loop with arrays of wires generate genvar gi; for (gi=0; gi<8; gi=gi+1) begin : gen_array_transform my_example_16_bit_transform_module u_mod ( .in (y[gi]), .out (z[gi]) ); end endgenerate // For loop with arrays integer index; always @(posedge clk, negedge rst_n) begin if (!rst_n) begin // reset arrayb for (index=0; index<256; index=index+1) begin mema[index] <= 8'h00; end end else begin // out of reset functional code end end
Conclusion
Verilog arrays are plain, simple, but quite limited. They really do not have many features beyond the basics of grouping signals together into a multidimensional structure. SystemVerilog arrays, on the other hand, are much more flexible and have a wide range of new features and uses. In the next article—SystemVerilog arrays, Synthesizable and Flexible—I will discuss the new features that have been added to SystemVerilog arrays and how to use them.
References
Sample Source Code
The accompany source code for this article is a toy example module and testbench that illustrates SystemVerilog array capabilities, including using an array as a port, assigning multi-dimensional arrays, and assigning slices of arrays. Download and run it to see how it works!
[lab_subscriber_download_form download_id=11].
In the initial array_name example, don’t you have the msb and lsb swapped around?
Hi Graham. You’re right! I’ve fixed the typo. Thanks for noticing the error.
what to do if i want to copy an array content to other array?
Is using a loop the only way to do so ?
Hi Priyansh. With plain Verilog-2005, yes that is the only way to do it. With SystemVerilog you can manipulate arrays much more easily, like copying slices, dimensions, entire arrays. See my post SystemVerilog Arrays, Flexible and Synthesizable.
If there’s no difference between array1[0:7] and array2[7:0], why does one have to put the lsb and msb?
Hi Stefan. I think internally depending on which way you define the array, it does potentially affect the location of where the data is placed (e.g. where array1[0] is located). But that will be transparent you when coding RTL as long as you use the indices consistently. SystemVerilog actually allows you to define an array with just array1[SIZE], which is the same as array1[0:SIZE-1].
Hey Jason
I have a doubt regarding 2D arrays in Verilog. Suppose I want a design which take two 2D arrays as inputs and gives an output as 2D array. When I tried to declare the input output ports as 2D arrays, it did not work at all.
I request you to kindly suggest me the way i can do my above said task in verilog.
Thanks in Advance…..
Hi. See an example I created on edaplayground here.
Hi Jason,
I want to instantiate FIFO block 256 times. How to write an array?
Thanks In Advance
Hi Chetana. If you want to instantiate a module multiple times in an array, you need to use a generate loop. See my article Verilog Generate Configurable Designs.
Hi sir..how can i form covariance matrix in verilog.sir please suggest coding.
Hi Jason,
I have a question regarding arrays and memory. I want to write the content of a 1D array into a specific location of a memory. But I’m not able to do this for some reason.
I request you to kindly suggest me the way i can do my above said task in verilog.
Thanks in Advance…
Hi Gautham. Sorry I don’t fully understand your question. A 1D array has multiple elements. How can you write that into one location of a memory? Or you mean you want to write it to multiple consecutive locations of the memory?
Hi Jason. Thank you for replying back. I’m sorry that the question is not very clear. Yes, I wanted to ask how to write data from a 1D array into consecutive locations of a memory in verilog.
Thank you…