Month: October 2015

One-hot State Machine in SystemVerilog – Reverse Case Statement

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Finite state machine (FSM) is one of the first topics taught in any digital design course, yet coding one is not as easy as first meets the eye. There are Moore and Mealy state machines, encoded and one-hot state encoding, one or two or three always block coding styles. Recently I was reviewing a coworker’s … Read more

SystemVerilog always_comb, always_ff. New and Improved.

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Verilog engineers will be familiar with using Verilog always to code recurring procedures like sequential logic (if not, refer to my article Verilog Always Block for RTL Modeling), and most will have used always @(*) to code combinational logic. SystemVerilog defines four forms of always procedures: always, always_comb, always_ff, always_latch. What do the three new … Read more