Comments on: SystemVerilog and Verilog X Optimism – Hardware-like X Propagation with Xprop https://www.verilogpro.com/x-propagation-with-vcs-xprop/ Verilog and Systemverilog Resources for Design and Verification Fri, 23 Dec 2022 01:45:16 +0000 hourly 1 https://wordpress.org/?v=6.5.2 By: Jason Yu https://www.verilogpro.com/x-propagation-with-vcs-xprop/#comment-8243 Fri, 23 Dec 2022 01:45:16 +0000 http://www.verilogpro.com/?p=45#comment-8243 In reply to Ferdous.

Not that I know of… In the past I had spent many hours hunting down exactly where the X originated from.

]]> By: Ferdous https://www.verilogpro.com/x-propagation-with-vcs-xprop/#comment-8241 Thu, 22 Dec 2022 09:03:24 +0000 http://www.verilogpro.com/?p=45#comment-8241 Is it possible to generate report that tell you where the x originated from?

]]> By: Sushant Jain https://www.verilogpro.com/x-propagation-with-vcs-xprop/#comment-2123 Wed, 08 Apr 2020 09:53:25 +0000 http://www.verilogpro.com/?p=45#comment-2123 Thank you Jason.
It really helped me understanding X-Prop simulations

]]> By: Prathyusha https://www.verilogpro.com/x-propagation-with-vcs-xprop/#comment-1374 Tue, 08 Jan 2019 11:23:09 +0000 http://www.verilogpro.com/?p=45#comment-1374 Hi,Jason!

I gave the SCOPE top.dut.BLK_XXX.ISO_XXX.module_name.

And I compile srun build-my DE(example peripheral)-lib-xprop.
And elaborate srun build-my DE(example peripheral)-xprop.

Then I ran my corresponding test-case.
Test is passed.

But I didn’t get any difference b/w normal simulation and xprop simulation.

Could please tell me where can we observed the difference?

]]> By: Jason Yu https://www.verilogpro.com/x-propagation-with-vcs-xprop/#comment-931 Thu, 24 May 2018 14:28:42 +0000 http://www.verilogpro.com/?p=45#comment-931 In reply to Nimit.

Hi Nimit. Unfortunately I haven’t written any article on UPF. Bit I would recommend Accellera’s video series on the basics. http://videos.accellera.org/upflowpower/index.html

]]> By: Nimit https://www.verilogpro.com/x-propagation-with-vcs-xprop/#comment-930 Wed, 23 May 2018 23:15:19 +0000 http://www.verilogpro.com/?p=45#comment-930 Hi Jason,
Excellent article.
Is there any article about UPF flow too, that you might have written.

]]> By: Jason Yu https://www.verilogpro.com/x-propagation-with-vcs-xprop/#comment-735 Sun, 07 Jan 2018 06:57:05 +0000 http://www.verilogpro.com/?p=45#comment-735 In reply to kanta.

Hi Kanta. You can enable xprop by following the instructions in this article to create the xprop configuration file, and to add the command line arguments.

]]> By: kanta https://www.verilogpro.com/x-propagation-with-vcs-xprop/#comment-734 Fri, 05 Jan 2018 13:20:20 +0000 http://www.verilogpro.com/?p=45#comment-734 Hi Jason,

how to enable the x-prop feature in VCS tool.

]]> By: Jason Yu https://www.verilogpro.com/x-propagation-with-vcs-xprop/#comment-639 Wed, 08 Nov 2017 16:03:23 +0000 http://www.verilogpro.com/?p=45#comment-639 In reply to anxu.

Hi, you also need to create and specify the xprop_config_file to indicate which design hierarchy to enable xprop. Give that a try.

]]> By: anxu https://www.verilogpro.com/x-propagation-with-vcs-xprop/#comment-636 Wed, 08 Nov 2017 11:48:22 +0000 http://www.verilogpro.com/?p=45#comment-636 how to use xprop?
i have a demo named test.v,and i type the following command to compile and simulate it.
#vcs -Xprop=tmerge test.v
#./simv
but i cannot get the report for xprop?
can you give me the details for it?please.thanks.

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