{"id":1,"name":"Jason Yu","url":"http:\/\/www.verilogpro.com","description":"Jason has 14 years' experience in the semiconductor industry, designing and verifying Solid State Drive controller SoC. His areas of work include microarchitecture and RTL design, dynamic and formal verification using UVM and Cadence JasperGold, and full-chip low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in any way.","link":"https:\/\/www.verilogpro.com\/author\/jasonkkygmail-com\/","slug":"jasonkkygmail-com","avatar_urls":{"24":"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=24&d=mm&r=g","48":"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=48&d=mm&r=g","96":"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g"},"meta":[],"yoast_head":"\n