{"id":11,"count":1,"description":"","link":"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/","name":"SystemVerilog Assertions (SVA)","slug":"systemverilog-assertions","taxonomy":"post_tag","meta":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v22.5 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>SystemVerilog Assertions (SVA) Archives - Verilog Pro<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"SystemVerilog Assertions (SVA) Archives - Verilog Pro\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/\" \/>\n<meta property=\"og:site_name\" content=\"Verilog Pro\" \/>\n<meta property=\"og:image\" content=\"http:\/\/www.verilogpro.com\/wp-content\/uploads\/2015\/09\/VLSIDesign-thumbnail.png\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:site\" content=\"@jasonkky\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"CollectionPage\",\"@id\":\"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/\",\"url\":\"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/\",\"name\":\"SystemVerilog Assertions (SVA) Archives - Verilog Pro\",\"isPartOf\":{\"@id\":\"https:\/\/www.verilogpro.com\/#website\"},\"breadcrumb\":{\"@id\":\"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/#breadcrumb\"},\"inLanguage\":\"en-US\"},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/www.verilogpro.com\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"SystemVerilog Assertions (SVA)\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.verilogpro.com\/#website\",\"url\":\"https:\/\/www.verilogpro.com\/\",\"name\":\"Verilog Pro\",\"description\":\"Verilog and Systemverilog Resources for Design and Verification\",\"publisher\":{\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.verilogpro.com\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"en-US\"},{\"@type\":[\"Person\",\"Organization\"],\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af\",\"name\":\"Jason Yu\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/\",\"url\":\"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g\",\"contentUrl\":\"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g\",\"caption\":\"Jason Yu\"},\"logo\":{\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/\"},\"description\":\"Jason has 14 years' experience in the semiconductor industry, designing and verifying Solid State Drive controller SoC. His areas of work include microarchitecture and RTL design, dynamic and formal verification using UVM and Cadence JasperGold, and full-chip low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in any way.\",\"sameAs\":[\"http:\/\/www.verilogpro.com\",\"https:\/\/ca.linkedin.com\/in\/jasonkky\",\"https:\/\/x.com\/jasonkky\"]}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"SystemVerilog Assertions (SVA) Archives - Verilog Pro","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/","og_locale":"en_US","og_type":"article","og_title":"SystemVerilog Assertions (SVA) Archives - Verilog Pro","og_url":"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/","og_site_name":"Verilog Pro","og_image":[{"url":"http:\/\/www.verilogpro.com\/wp-content\/uploads\/2015\/09\/VLSIDesign-thumbnail.png"}],"twitter_card":"summary_large_image","twitter_site":"@jasonkky","schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"CollectionPage","@id":"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/","url":"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/","name":"SystemVerilog Assertions (SVA) Archives - Verilog Pro","isPartOf":{"@id":"https:\/\/www.verilogpro.com\/#website"},"breadcrumb":{"@id":"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/#breadcrumb"},"inLanguage":"en-US"},{"@type":"BreadcrumbList","@id":"https:\/\/www.verilogpro.com\/tag\/systemverilog-assertions\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.verilogpro.com\/"},{"@type":"ListItem","position":2,"name":"SystemVerilog Assertions (SVA)"}]},{"@type":"WebSite","@id":"https:\/\/www.verilogpro.com\/#website","url":"https:\/\/www.verilogpro.com\/","name":"Verilog Pro","description":"Verilog and Systemverilog Resources for Design and Verification","publisher":{"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.verilogpro.com\/?s={search_term_string}"},"query-input":"required name=search_term_string"}],"inLanguage":"en-US"},{"@type":["Person","Organization"],"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af","name":"Jason Yu","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/","url":"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g","caption":"Jason Yu"},"logo":{"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/"},"description":"Jason has 14 years' experience in the semiconductor industry, designing and verifying Solid State Drive controller SoC. His areas of work include microarchitecture and RTL design, dynamic and formal verification using UVM and Cadence JasperGold, and full-chip low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in any way.","sameAs":["http:\/\/www.verilogpro.com","https:\/\/ca.linkedin.com\/in\/jasonkky","https:\/\/x.com\/jasonkky"]}]}},"_links":{"self":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/tags\/11"}],"collection":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/tags"}],"about":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/taxonomies\/post_tag"}],"wp:post_type":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/posts?tags=11"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}