{"id":96,"date":"2015-09-13T18:01:11","date_gmt":"2015-09-13T18:01:11","guid":{"rendered":"http:\/\/www.verilogpro.com\/?p=96"},"modified":"2022-06-27T00:43:12","modified_gmt":"2022-06-27T07:43:12","slug":"verilog-case-casez-casex","status":"publish","type":"post","link":"https:\/\/www.verilogpro.com\/verilog-case-casez-casex\/","title":{"rendered":"Verilog twins: case, casez, casex. Which Should I Use?"},"content":{"rendered":"\n<p>The Verilog <b>case<\/b> statement is a convenient structure to code various logic like decoders, encoders, onehot state machines. Verilog defines three versions of the case statement: <b>case<\/b>, <b>casez<\/b>, <b>casex<\/b>. Not only is it easy to confuse them, but there are subtleties between them that can trip up even experienced coders. In this article I will highlight the identifying features of each of the twins, and discuss when each should be used.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Basic Verilog Case Statement<\/h3>\n\n\n\n<p>Let&#8217;s start by reviewing the basic <b>case<\/b> statement:<\/p>\n\n\n\n<pre class=\"wp-block-preformatted lang:default decode:true\">case (case_expression) \/\/ case statement header\n  case_item_1 : begin\n    case_statement_1a;\n    case_statement_1b;\n  end\n  case_item_2 : case_statement_2;\n  default     : case_statement_default;\nendcase<\/pre>\n\n\n\n<p>A case statement has the following parts:<\/p>\n\n\n\n<ul><li><i>Case statement header<\/i>&#8212;consists of the <b>case<\/b>, <b>casez<\/b>, or <b>casex<\/b> keyword followed by <i>case expression<\/i><\/li><li><i>Case expression<\/i>&#8212;the expression in parentheses immediately following the <b>case<\/b> keyword. Valid expressions include constants (e.g. 1&#8217;b1), an expression that evaluates to a constant, or a vector<\/li><li><i>Case item<\/i>&#8212;the expression that is compared against the <i>case expression<\/i>. Note that C-style <b>break<\/b> is implied following each <i>case item statement<\/i><\/li><li><i>Case item statement<\/i>&#8212;one or more statements that is executed if the <i>case item<\/i> matches the current <i>case expression<\/i>. If more than one statement is required, they must be enclosed with <b>begin&#8230;end<\/b><\/li><li><i>Case default<\/i>&#8212;optional, but can include statements to be executed if none of the defined <i>case items<\/i> match the current <i>case expression<\/i><\/li><\/ul>\n\n\n\n<script async=\"\" src=\"https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811\" crossorigin=\"anonymous\"><\/script>\n<ins class=\"adsbygoogle\" style=\"display:block; text-align:center;\" data-ad-layout=\"in-article\" data-ad-format=\"fluid\" data-ad-client=\"ca-pub-9720137902431811\" data-ad-slot=\"7477548078\"><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n\n\n\n<h3 class=\"wp-block-heading\">Wildcard Case Statement: casez<\/h3>\n\n\n\n<p>The plain <b>case<\/b> statement is simple but rigid&#8212;everything must be explicitly coded. In some situations, you may want to specify a <i>case item<\/i> that can match multiple <i>case expressions<\/i>. This is where &#8220;wildcard&#8221; <i>case expressions<\/i> <b>casez<\/b> and <b>casex<\/b> come in. <b>casez<\/b> allows &#8220;Z&#8221; and &#8220;?&#8221; to be treated as don&#8217;t care values in either the <i>case expression<\/i> and\/or the <i>case item<\/i> when doing case comparison. For example, a <i>case item<\/i> 2&#8217;b1? (or 2&#8217;b1Z) in a <b>casez<\/b> statement can match <i>case expression<\/i> of 2&#8217;b10, 2&#8217;b11, 2&#8217;b1X, 2&#8217;b1Z. It is generally recommended to use &#8220;?&#8221; characters instead of &#8220;Z&#8221; characters in the <i>case item<\/i> to indicate don&#8217;t care bits.<\/p>\n\n\n\n<p>Verilog &#8220;wildcard&#8221; <i>case statements<\/i> can have overlapping <i>case items<\/i>. If more than one <i>case item<\/i> can match a <i>case expression<\/i>, the first matching <i>case item<\/i> has priority. Thus, priority logic can be inferred from a case statement. The following code snippet illustrates how <b>casez<\/b> can be used to code priority logic. It simulates and synthesizes correctly as a priority decoder.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted lang:default decode:true\">always @(irq) begin\n  {int2, int1, int0} = 3'b000;\n  casez (irq)\n    3'b1?? : int2 = 1'b1;\n    3'b?1? : int1 = 1'b1;\n    3'b??1 : int0 = 1'b1;\n    default: {int2, int1, int0} = 3'b000;\n  endcase\nend<\/pre>\n\n\n\n<div class=\"wp-block-image\"><figure class=\"aligncenter\"><a href=\"https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2015\/10\/verilog-casez-priority-decoder.png\"><img loading=\"lazy\" decoding=\"async\" width=\"500\" height=\"200\" src=\"https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2015\/10\/verilog-casez-priority-decoder.png?resize=500%2C200\" alt=\"Verilog casez priority decoder\" class=\"wp-image-194\" srcset=\"https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2015\/10\/verilog-casez-priority-decoder.png?w=500&amp;ssl=1 500w, https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2015\/10\/verilog-casez-priority-decoder.png?resize=300%2C120&amp;ssl=1 300w\" sizes=\"(max-width: 500px) 100vw, 500px\" data-recalc-dims=\"1\" \/><\/a><\/figure><\/div>\n\n\n\n<p>The logic will look something like this:<br><\/p>\n\n\n\n<p>Even though this may seem an elegant way to code a priority decoder, the priority intention may only be apparent to the most experienced coders. Therefore, it is generally recommended to code priority logic using the more explicit <b>if&#8230;else<\/b> statement to clearly convey the intention.<\/p>\n\n\n\n<p>While wildcard case comparison can be useful, it also has its dangers. Imagine a potentially dangerous <b>casez<\/b> statement where the <i>case expression<\/i> is a vector and one bit resolves to a &#8220;Z&#8221;, perhaps due to a mistakenly unconnected input. That expression will match a <i>case item<\/i> with any value for the &#8220;Z&#8221; bit! To put in more concrete terms, if the LSB of <i>irq<\/i> in the above code snippet is unconnected such that the <i>case expression<\/i> evaluates to 3&#8217;b00Z, the third <i>case item<\/i> will still match and <i>int0<\/i> will be set to 1, potentially masking a bug!<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Even wilder: casex<\/h3>\n\n\n\n<p>Now that we understand the usage and dangers of <b>casez<\/b>, it is straight-forward to extend the discussion to <b>casex<\/b>. <b>casex<\/b> allows &#8220;Z&#8221;, &#8220;?&#8221;, and &#8220;X&#8221; to be treated as don&#8217;t care values in either the <i>case expression<\/i> and\/or the <i>case item<\/i> when doing case comparison. That means, everything we discussed for <b>casez<\/b> also applies for <b>casex<\/b>, plus &#8220;X&#8221; is now also a wildcard. In my previous article on <a href=\"http:\/\/www.verilogpro.com\/systemverilog-verilog-x-optimism\/\">Verilog X Optimism<\/a> I discussed how X&#8217;s can propagate around a design and mask design issues. These propagated X&#8217;s can easily cause problems when combined with <b>casex<\/b> statements. To avoid these problems, the recommendation from <a href=\"http:\/\/www.verilog.org\/vlog-synth\/Mills_Final.pdf\">RTL Coding Styles That Yield Simulation and Synthesis Mismatches<\/a> is not to use <b>casex<\/b> at all for synthesizable code.<\/p>\n\n\n\n<p>Verilog <b>case<\/b>, <b>casez<\/b>, <b>casex<\/b> each has its place and use cases. Understanding the differences between them is key to using them correctly and avoiding bugs. It may also help you in your next job interview \ud83d\ude42<\/p>\n\n\n\n<p>Have you come across any improper usage of these constructs? What are your recommendations for using them, especially <b>casex<\/b>? Leave a comment below!<\/p>\n\n\n\n<script async=\"\" src=\"https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811\" crossorigin=\"anonymous\"><\/script>\n<ins class=\"adsbygoogle\" style=\"display:block; text-align:center;\" data-ad-layout=\"in-article\" data-ad-format=\"fluid\" data-ad-client=\"ca-pub-9720137902431811\" data-ad-slot=\"7477548078\"><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n\n\n\n<h3 class=\"wp-block-heading\">SystemVerilog Unique Case<\/h3>\n\n\n\n<p>SystemVerilog adds a possible <i>unique<\/i> modifier to case statements. How does that change the behaviour? Head over to my post <a href=\"http:\/\/www.verilogpro.com\/systemverilog-unique-priority\/\">SystemVerilog Unique And Priority &#8211; How Do I Use Them?<\/a><\/p>\n\n\n\n<h3 class=\"wp-block-heading\">References<\/h3>\n\n\n\n<ol><li><a href=\"http:\/\/www.verilog.org\/vlog-synth\/Mills_Final.pdf\">RTL Coding Styles That Yield Simulation and Synthesis Mismatches<\/a><\/li><li><a href=\"http:\/\/www.sunburst-design.com\/papers\/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf\">&#8220;full_case parallel_case&#8221;, the Evil Twins of Verilog Synthesis<\/a><\/li><\/ol>\n\n\n\n<h3 class=\"wp-block-heading\">Quiz and Sample Source Code<\/h3>\n\n\n\n<p>Now it&#8217;s time for a quiz! How will each of the following variations of case statement behave when the case expression<\/p>\n\n\n\n<ol><li>matches one of the non-default case items<\/li><li>does not match any non-default case item<\/li><li>contains all X&#8217;s (e.g. if the signal comes from an uninitialized memory)<\/li><li>contains all Z&#8217;s (e.g. if the signal is unconnected)<\/li><li>contains a single bit X<\/li><li>contains a single bit Z<\/li><\/ol>\n\n\n\n<p>Case statement variations:<\/p>\n\n\n\n<ol><li>Plain case statement<\/li><li>Plain case with default case<\/li><li>Casez<\/li><li>Casez with default case<\/li><li>Casex<\/li><li>Casex with default case<\/li><li>Unique case<\/li><li>Unique case with default case<\/li><li>Unique casez<\/li><li>Unique casex<\/li><\/ol>\n\n\n\n<p>Stumped? Download the executable source code to find out the answer!<\/p>\n\n\n<p>[lab_subscriber_download_form download_id=7]<\/p>\n\n\n\n\n\n\n<script async src=\"https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811\"\n     crossorigin=\"anonymous\"><\/script>\n<ins class=\"adsbygoogle\"\n     style=\"display:block\"\n     data-ad-format=\"autorelaxed\"\n     data-ad-client=\"ca-pub-9720137902431811\"\n     data-ad-slot=\"3587260091\"><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n","protected":false},"excerpt":{"rendered":"<p>The Verilog case statement is a convenient structure to code various logic like decoders, encoders, onehot state machines. Verilog defines three versions of the case statement: case, casez, casex. Not only is it easy to confuse them, but there are subtleties between them that can trip up even experienced coders. In this article I will &#8230; <a title=\"Verilog twins: case, casez, casex. Which Should I Use?\" class=\"read-more\" href=\"https:\/\/www.verilogpro.com\/verilog-case-casez-casex\/\" aria-label=\"More on Verilog twins: case, casez, casex. Which Should I Use?\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"jetpack_post_was_ever_published":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":true,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"footnotes":"","_jetpack_memberships_contains_paid_content":false,"jetpack_publicize_message":"Case, casex, casez","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":true,"jetpack_social_options":{"image_generator_settings":{"template":"highway","enabled":false}}},"categories":[12],"tags":[16,17],"jetpack_publicize_connections":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v22.6 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Verilog twins: case, casez, casex - Verilog Pro<\/title>\n<meta name=\"description\" content=\"Verilog defines three different versions of case statement: case, casez, casex. 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His areas of work include microarchitecture and RTL design, dynamic and formal verification using UVM and Cadence JasperGold, and full-chip low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in any way.","sameAs":["http:\/\/www.verilogpro.com","https:\/\/ca.linkedin.com\/in\/jasonkky","https:\/\/x.com\/jasonkky"],"url":"https:\/\/www.verilogpro.com\/author\/jasonkkygmail-com\/"}]}},"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"jetpack_shortlink":"https:\/\/wp.me\/p6Du8T-1y","jetpack-related-posts":[],"_links":{"self":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/posts\/96"}],"collection":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/comments?post=96"}],"version-history":[{"count":37,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/posts\/96\/revisions"}],"predecessor-version":[{"id":836,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/posts\/96\/revisions\/836"}],"wp:attachment":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/media?parent=96"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/categories?post=96"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/tags?post=96"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}