For this article, I decided to take a quick pause from Verilog, to write an article on a topic that I had been researching the past few months. You have probably come across the term “chiplet”, and may be wondering what this latest trend in SoC design is about. In this article, I will explore some of the background topics and technologies around chiplet based designs, and give you many links to follow to find out more. I hope you find this topic equally interesting as Verilog coding. Here we go!<\/p>\n\n\n\n
Today’s complex SoCs are approaching (and in some cases already exceeded) the physical limit of how large a single silicon die can be manufactured. This limit is called the reticle limit. According to article in Protocol<\/a>,<\/p>\n\n\n\n But big die sizes create big problems. One fundamental issue is that it\u2019s currently impossible to print a chip larger than the blueprint used in the photolithography stage of chip manufacturing, called a photomask. Because of technical limits, the beam of light shining through the photomask to reproduce the blueprint onto the silicon wafer cannot print chips larger than about 850 square millimeters.<\/p>Chiplets helped save AMD. They might also help save Moore\u2019s law and head off an energy crisis. Protocol, July 20 2022<\/cite><\/blockquote>\n\n\n\n Therefore without breaking up a design into multiple dies (or multiple chiplet), engineers simply will not be able to design some cutting edge SoCs.<\/p>\n\n\n\n