{"id":723,"date":"2022-04-13T08:00:00","date_gmt":"2022-04-13T15:00:00","guid":{"rendered":"https:\/\/www.verilogpro.com\/?p=723"},"modified":"2022-06-27T00:37:56","modified_gmt":"2022-06-27T07:37:56","slug":"verilog-always-block","status":"publish","type":"post","link":"https:\/\/www.verilogpro.com\/verilog-always-block\/","title":{"rendered":"Verilog Always Block for RTL Modeling"},"content":{"rendered":"\n<p>This article is going to introduce the Verilog always block&#8212;one of the most basic constructs that has existed since the very beginning of Verilog (IEEE standard 1364-1995)&#8212;relate it to some other introductory constructs, and use them to write some simple hardware logic.<\/p>\n\n\n\n<p>After a long hiatus, I&#8217;m picking up the proverbial pen again and writing some Verilog articles! I have a new goal to create a series of articles to help new engineers transition from &#8220;textbook knowledge&#8221; to real world knowledge needed to become a digital design engineer. You&#8217;ll see some new articles on basic concepts, as well as intermediate level concepts similar to my previous articles. Hope you find these new articles useful for your career! Let&#8217;s get started!<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Verilog Always Block In a Nutshell<\/h2>\n\n\n\n<p>Verilog behaviour models (RTL design\/model is a class of behavioural models) contain procedural statements that control the simulation, and manipulate variables to model hardware circuitry and data flow. The Verilog always block is a procedural statement that starts an activity flow. Each Verilog always block starts a separate activity flow. All of the activity flows are concurrent to model the inherent concurrence of hardware. Each Verilog always block repeats continuously throughout the duration of the simulation, executing the statements defined in its procedure. Its activity ceases only when the simulation is terminated.<\/p>\n\n\n\n<script async=\"\" src=\"https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811\" crossorigin=\"anonymous\"><\/script>\n<ins class=\"adsbygoogle\" style=\"display:block; text-align:center;\" data-ad-layout=\"in-article\" data-ad-format=\"fluid\" data-ad-client=\"ca-pub-9720137902431811\" data-ad-slot=\"7477548078\"><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n\n\n\n<h2 class=\"wp-block-heading\">An Infinite Loop?<\/h2>\n\n\n\n<p>The Verilog always block essentially describes an infinite loop. Without some form of timing control to avoid a zero-delay infinite loop, and allow simulation time to advance, a simulation deadlock condition can be created (read: a simulation hang). The following code, for example, creates such a zero-delay infinite loop.<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>always areg = ~areg;<\/code><\/pre>\n\n\n\n<p>If there is a Verilog always block with no timing control, your simulation will look as though it has hung, and will not advance in time. So let&#8217;s add a timing control to make the code more useful:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>always #half_period clk = ~clk;<\/code><\/pre>\n\n\n\n<p>Now this becomes a potentially useful statement. It causes the <em>clk<\/em> signal to toggle its polarity at a delay of <em>half_period<\/em>. If you haven&#8217;t noticed already, it can be used to create a continuously toggling clock stimulus in a simulation.<\/p>\n\n\n\n<p>The &#8220;#&#8221; is formally called a delay control. It causes the simulation to insert the specified delay (to that procedural block) where the &#8220;#&#8221; is written.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Timing Control with Event Expression (Sensitivity List)<\/h2>\n\n\n\n<p>Another way to provide a timing control is in the form of a Verilog event expression. The syntax of Verilog event expression is &#8220;<em>@(event_expression)<\/em>&#8220;. For the procedural block that contains the Verilog event expression, it causes the simulator to wait until the <em>event_expression<\/em> has occurred before continuing execution of that procedural block. When used together with a Verilog always block, it adds the necessary timing control to make the Verilog always block useful to model hardware. The SystemVerilog standards (IEEE 1800-2005 onwards) also describe the event expression, when used to trigger a Verilog always block, as a &#8220;sensitivity list&#8221;.<\/p>\n\n\n\n<p>The event expression (or sensitivity list) can contain multiple signals. Each signal is separated by the keyword &#8220;or&#8221;. The following Verilog always block describes a simple OR gate with inputs <em>A<\/em> and <em>B<\/em>, and output <em>C<\/em>. This code tells the simulator to re-evaluate the value of output <em>C<\/em>, whenever the signal <em>A<\/em> or <em>B<\/em> changes. It is not entirely straightforward, but you can see how this essentially describes the behaviour of an OR gate in simulation.<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>always @(A or B)\n    C = A | B;<\/code><\/pre>\n\n\n\n<h2 class=\"wp-block-heading\">Modelling Hardware Logic with Verilog Always Block<\/h2>\n\n\n\n<p>Combining these ideas brings us to the more common usage of Verilog always block&#8212;together with an event expression.<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>always @(<em>event_expression<\/em>)\n<em>    single_statement<\/em>;\n\nalways @(<em>event_expression<\/em>)\nbegin\n<em>    multiple_statements<\/em>;\nend<\/code><\/pre>\n\n\n\n<p>For hardware modeling, the Verilog event expression is typically specified in one of two forms:<\/p>\n\n\n\n<ul><li>Sequential logic: execution triggered based on a clock event (and frequently a reset event)<\/li><li>Combinational logic: execution triggered based on the inputs to the logic (i.e. nets and variables on the right hand side of an assignment statement)<\/li><\/ul>\n\n\n\n<script async=\"\" src=\"https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811\" crossorigin=\"anonymous\"><\/script>\n<ins class=\"adsbygoogle\" style=\"display:block; text-align:center;\" data-ad-layout=\"in-article\" data-ad-format=\"fluid\" data-ad-client=\"ca-pub-9720137902431811\" data-ad-slot=\"7477548078\"><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n\n\n\n<h3 class=\"wp-block-heading\">Modeling Sequential Logic<\/h3>\n\n\n\n<p>A typical event expression for a flip-flop based design is &#8220;@(posedge <em>clock_name<\/em>)&#8221;. This tells the simulator to only evaluate the Verilog always block when the <em>clock_name<\/em> signal makes a positive edge transition (0-&gt;1), which is how a flip-flop based design is constructed. Without the &#8220;posedge&#8221; keyword, the Verilog always block will trigger on any transition of the <em>clock_name<\/em> signal, both positive and negative.<\/p>\n\n\n\n<p>The following code describes a flip-flop with input <em>d<\/em> and output <em>q<\/em>, clocked by positive edge of <em>clk<\/em> (with no reset):<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>always @(posedge clk)\n    q &lt;= d;<\/code><\/pre>\n\n\n\n<p>Let&#8217;s make it a more complete flip-flop design by also adding a reset, namely an asynchronous reset. An asynchronous reset means the reset will occur even without the presence of a clock. An asynchronous reset is modeled by adding the reset signal also to the sensitivity list. This will cause the simulator to re-evaluate this Verilog always block when the reset signal transitions, irrespective of whether the <em>clk<\/em> signal transitions (which is what an asynchronous reset means). The Verilog event expression &#8220;@(negedge rst_n)&#8221; makes the reset active low (trigger an evaluation when <em>rst_n<\/em> transitions 1-&gt;0), and the &#8220;if&#8221; statement specifies a reset value for the flip-flop. The following code describes the same flip-flop, now with an active-low asynchronous reset (<em>rst_n<\/em>) that will reset the flip-flop output <em>q<\/em> to 0 when the reset is asserted (when <em>rst_n<\/em> transitions 1-&gt;0).<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>always @(posedge clk or negedge rst_n)\n    if (!rst_n)\n        q &lt;= 1'b0;\n    else\n        q &lt;= d;<\/code><\/pre>\n\n\n\n<p>To describe two flip flops, you can write them as two separate Verilog always block. Let&#8217;s make it more interesting and put them in series into a two-stage pipeline. First the diagram, then the code.<\/p>\n\n\n\n<figure class=\"wp-block-image size-full\"><a href=\"https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2022\/04\/verilog_always_flipflop-1.png?ssl=1\"><img loading=\"lazy\" decoding=\"async\" width=\"977\" height=\"407\" src=\"https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2022\/04\/verilog_always_flipflop-1.png?resize=977%2C407&#038;ssl=1\" alt=\"Two stage pipelined D flip flops\" class=\"wp-image-735\" srcset=\"https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2022\/04\/verilog_always_flipflop-1.png?w=977&amp;ssl=1 977w, https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2022\/04\/verilog_always_flipflop-1.png?resize=300%2C125&amp;ssl=1 300w, https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2022\/04\/verilog_always_flipflop-1.png?resize=768%2C320&amp;ssl=1 768w\" sizes=\"(max-width: 977px) 100vw, 977px\" data-recalc-dims=\"1\" \/><\/a><figcaption>Two stage pipelined D flip flops<\/figcaption><\/figure>\n\n\n\n<pre class=\"wp-block-code\"><code>always @(posedge clk or negedge rst_n)\n    if (!rst_n)\n        q1 &lt;= 1'b0;\n    else\n        q1 &lt;= d1;\n\nalways @(posedge clk or negedge rst_n)\n    if (!rst_n)\n        q2 &lt;= 1'b0;\n    else\n        q2 &lt;= q1;<\/code><\/pre>\n\n\n\n<p>Or you can also write it as one Verilog always block.<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>always @(posedge clk or negedge rst_n)\n    if (!rst_n) begin\n        q1 &lt;= 1'b0;\n        q2 &lt;= 1'b0;\n    end\n    else begin\n        q1 &lt;= d1;\n        q2 &lt;= q1;\n    end<\/code><\/pre>\n\n\n\n<p>When there are multiple Verilog always blocks, there is no implied order of execution between them. There is also no limit to the number of always constructs that can be defined in a module.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Modeling Combinational Logic<\/h3>\n\n\n\n<p>The Verilog always block can also model combinational logic, but it is a bit less straight forward to understand. A physical implementation of a combinational circuit obviously operates continuously, sampling the inputs and calculating the resulting outputs. A simulator, however, cannot execute a logical statement &#8220;continuously&#8221;, without causing the zero-delay infinite loop described at the beginning of the article. Therefore to simulate combinational circuit, we have to define specific events at which the simulator should execute procedures, while maintaining correct behaviour.<\/p>\n\n\n\n<p>The simple answer is, to model combinational circuit, the sensitivity list needs to contain all the inputs to the circuit (all the variables on the right hand side of the assignment). The following code describes a combinational AND gate using a Verilog always block.<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>always @(A or B)\n    C = A &amp; B;<\/code><\/pre>\n\n\n\n<script async=\"\" src=\"https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811\" crossorigin=\"anonymous\"><\/script>\n<ins class=\"adsbygoogle\" style=\"display:block; text-align:center;\" data-ad-layout=\"in-article\" data-ad-format=\"fluid\" data-ad-client=\"ca-pub-9720137902431811\" data-ad-slot=\"7477548078\"><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n\n\n\n<h2 class=\"wp-block-heading\">More on Event Expression with Verilog Always Block<\/h2>\n\n\n\n<p>Here are a few more tips with using Verilog event expression with Verilog always block.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Using Comma in Event Expression<\/h3>\n\n\n\n<p>Verilog-2001 standard introduced the use of comma &#8220;,&#8221; to separate items in the event expression. Prior to that with the original Verilog-1995 standard, the separate items in the event expression must be separated by the keyword &#8220;or&#8221;. I have used the Verilog-1995 syntax in all the code examples so far. But here is the same flip-flop code example written with the Verilog-2001 syntax.<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>always @(posedge clk, negedge rst_n)\n    if (!rst_n)\n        q &lt;= 1'b0;\n    else\n        q &lt;= d;<\/code><\/pre>\n\n\n\n<p>Personally I prefer the Verilog-2001 syntax. That is how I write my code.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Implicit Event Expression @* or @(*)<\/h3>\n\n\n\n<p>Sensitivity list is a frequent source of bugs in a Verilog design\/model. A deeper discussion of common pitfalls will be the subject of a future article. The standard writers wanted to simplify the usage of the the sensitivity list somewhat in Verilog-2001, so they added the &#8220;implicit event_expression list&#8221; syntax to simplify using Verilog always block, at least to describe combinational logic. Using an implicit event expression list, the AND gate combinational logic can be rewritten as follows.<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>always @*\n    C = A &amp; B;\n\nalways @(*)\n    C = A &amp; B;<\/code><\/pre>\n\n\n\n<p>More precisely, the &#8220;@*&#8221; and &#8220;@(*)&#8221; syntax will add all nets and variables that appear in the (right hand side of a) statement to the event expression, with some exceptions.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Verilog Always Block, Evolution to SystemVerilog always_comb and always_ff<\/h3>\n\n\n\n<p>SystemVerilog adds several new syntax in addition to the Verilog always block, primarily to address the exceptions noted above. You can read more about these constructs in my article <a href=\"https:\/\/www.verilogpro.com\/systemverilog-always_comb-always_ff\/\">SystemVerilog always_comb, always_ff<\/a>.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Conclusion<\/h2>\n\n\n\n<p id=\"verilog-always-block\">Verilog always block is one of the four procedural statements in the original Verilog language. It can be used to model testbench stimulus as well as hardware design. The Verilog always block is essentially an infinite loop. However, when combined with a Verilog event expression, it can be used to model combinational and sequential logic. SystemVerilog adds several new versions of &#8220;always&#8221;, in addition to Verilog always block, to address some limitations and pitfalls of the original Verilog syntax.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">References<\/h2>\n\n\n\n<ul><li><a href=\"https:\/\/ieeexplore.ieee.org\/document\/803556\">1364-1995 &#8211; IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language<\/a> (the original Verilog standard! Commonly called Verilog-1995)<\/li><li><a href=\"https:\/\/ieeexplore.ieee.org\/document\/954909\">1364-2001 &#8211; IEEE Standard Verilog Hardware Description Language<\/a> (commonly called Verilog-2001)<\/li><li><a href=\"https:\/\/ieeexplore.ieee.org\/document\/1560791\">1800-2005 &#8211; IEEE Standard for SystemVerilog: Unified Hardware Design, Specification and Verification Language<\/a> (the first SystemVerilog standard)<\/li><\/ul>\n\n\n\n\n\n\n<script async src=\"https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811\"\n     crossorigin=\"anonymous\"><\/script>\n<ins class=\"adsbygoogle\"\n     style=\"display:block\"\n     data-ad-format=\"autorelaxed\"\n     data-ad-client=\"ca-pub-9720137902431811\"\n     data-ad-slot=\"3587260091\"><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n","protected":false},"excerpt":{"rendered":"<p>Verilog always block is a procedural statement that starts an activity flow. It is essentially an infinite loop. However, when combined with a Verilog event expression, it can be used to model combinational and sequential logic.<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"jetpack_post_was_ever_published":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_memberships_contains_paid_content":false,"footnotes":"","jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":true,"jetpack_social_options":{"image_generator_settings":{"template":"highway","enabled":false}}},"categories":[3,12],"tags":[39,42,40],"jetpack_publicize_connections":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v22.6 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Verilog Always Block for RTL Modeling - Verilog Pro<\/title>\n<meta name=\"description\" content=\"Verilog always block is a procedural statement that starts an activity flow. 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