Verilog generate statement is a powerful construct for writing configurable, synthesizable RTL. It can be used to create multiple instantiations of modules and code, or conditionally instantiate blocks of code. However, many Verilog programmers often have questions about how to use Verilog generate effectively. In this article, I will review the usage of three forms of Verilog generate—generate loop, if-generate, and case-generate.<\/p>\n\n\n\n
There are two kinds of Verilog generate constructs. Generate loop constructs allow a block of code to be instantiated multiple times, controlled by a variable index. Conditional generate constructs select at most one block of code between multiple blocks. Conditional generate constructs include if-generate and case-generate forms.<\/p>\n\n\n\n
Verilog generate constructs are evaluated at elaboration, which occurs after parsing the HDL (and preprocessor), but before simulation begins. Therefore all expressions within generate constructs must be constant expressions, deterministic at elaboration time. For example, generate constructs can be affected by values from parameters, but not by dynamic variables.<\/p>\n\n\n\n
A Verilog generate block creates a new scope and a new level of hierarchy, almost like instantiating a module. This sometimes causes confusion when trying to write a hierarchical reference to signals or modules within a generate block, so it is something to keep in mind.<\/p>\n\n\n\n
Use of the keywords generate<\/strong> and endgenerate<\/strong> (and begin<\/strong>\/end<\/strong>) is actually optional. If they are used, then they define a generate region<\/em>. Generate regions can only occur directly within a module, and they cannot nest. For readability, I like to use the generate<\/strong> and endgenerate<\/strong> keywords.<\/p>\n\n\n\n