{"id":607,"date":"2017-10-10T10:00:44","date_gmt":"2017-10-10T17:00:44","guid":{"rendered":"http:\/\/www.verilogpro.com\/?p=607"},"modified":"2022-06-26T00:08:33","modified_gmt":"2022-06-26T07:08:33","slug":"systemverilog-arrays-synthesizable","status":"publish","type":"post","link":"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/","title":{"rendered":"SystemVerilog Arrays, Flexible and Synthesizable"},"content":{"rendered":"\n<p>In my last article on plain old <a href=\"http:\/\/www.verilogpro.com\/verilog-arrays-plain-simple\/\">Verilog Arrays<\/a>, I discussed their very limited feature set. In comparison, SystemVerilog arrays have greatly expanded capabilities both for writing synthesizable RTL, and for writing non-synthesizable test benches. In this article, we&#8217;ll take a look at the synthesizable features of SystemVerilog Arrays we can use when writing design RTL.<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Packed vs Unpacked SystemVerilog Arrays<\/h2>\n\n\n\n<p>Verilog had only one type of array. SystemVerilog arrays can be either <em>packed<\/em> or <em>unpacked<\/em>. Packed array refers to dimensions declared after the type and before the data identifier name. Unpacked array refers to the dimensions declared after the data identifier name.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted lang:default decode:true\">bit [7:0] c1;         \/\/ packed array of scalar bit\nreal      u [7:0];    \/\/ unpacked array of real\n\nint Array[0:7][0:31]; \/\/ unpacked array declaration using ranges\nint Array[8][32];     \/\/ unpacked array declaration using sizes<\/pre>\n\n\n\n<script async=\"\" src=\"https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811\" crossorigin=\"anonymous\"><\/script>\n<ins class=\"adsbygoogle\" style=\"display:block; text-align:center;\" data-ad-layout=\"in-article\" data-ad-format=\"fluid\" data-ad-client=\"ca-pub-9720137902431811\" data-ad-slot=\"7477548078\"><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n\n\n\n<h3 class=\"wp-block-heading\">Packed Arrays<\/h3>\n\n\n\n<p>A one-dimensional packed array is also called a vector. Packed array divides a vector into subfields, which can be accessed as array elements. A packed array is guaranteed to be represented as a contiguous set of bits in simulation and synthesis.<\/p>\n\n\n\n<p>Packed arrays can be made of only the single bit data types (<strong>bit<\/strong>, <strong>logic<\/strong>, <strong>reg<\/strong>), enumerated types, and other packed arrays and packed structures. This also means you cannot have packed arrays of integer types with predefined widths (e.g. a packed array of <strong>byte<\/strong>).<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Unpacked arrays<\/h3>\n\n\n\n<p>Unpacked arrays can be made of any data type. Each fixed-size dimension is represented by an address range, such as [0:1023], or a single positive number to specify the size of a fixed-size unpacked array, such as [1024]. The notation [size] is equivalent to [0:size-1].<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Indexing and Slicing SystemVerilog Arrays<\/h3>\n\n\n\n<p>Verilog arrays could only be accessed one element at a time. In SystemVerilog arrays, you can also select one or more contiguous elements of an array. This is called a <em>slice<\/em>. An array slice can only apply to one dimension; other dimensions must have single index values in an expression.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Multidimensional Arrays<\/h3>\n\n\n\n<p>Multidimensional arrays can be declared with both packed and unpacked dimensions. Creating a multidimensional packed array is analogous to slicing up a continuous vector into multiple dimensions.<\/p>\n\n\n\n<p>When an array has multiple dimensions that can be logically grouped, it is a good idea to use <strong>typedef<\/strong> to define the multidimensional array in stages to enhance readability. But notice the order of the dimensions become a little confusing.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted lang:default decode:true\">bit [3:0] [7:0] joe [0:9] \/\/ 10 elements of 4 8-bit bytes\n                          \/\/ (each element packed into 32 bits)\n\ntypedef bit [4:0] bsix;   \/\/ multiple packed dimensions with typedef\nbsix [9:0] v5;            \/\/ equivalent to bit[9:0][4:0] v5 - thanks Yunsung!\n\ntypedef bsix mem_type [0:3]; \/\/ array of four unpacked 'bsix' elements\nmem_type ba [0:7];           \/\/ array of eight unpacked 'mem_type' elements\n                             \/\/ equivalent to bit[4:0] ba [0:7][0:3] - thanks Yunsung!\n<\/pre>\n\n\n\n<h2 class=\"wp-block-heading\">SystemVerilog Array Operations<\/h2>\n\n\n\n<p>SystemVerilog arrays support many more operations than their traditional Verilog counterparts.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">+: and -: Notation<\/h3>\n\n\n\n<p>When accessing a range of indices (a <i>slice<\/i>) of a SystemVerilog array, you can specify a variable slice by using the [start+:increment width] and [start-:decrement width] notations. They are simpler than needing to calculate the exact start and end indices when selecting a variable slice. The increment\/decrement width must be a constant.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted lang:default decode:true\">bit signed [31:0] busA [7:0]; \/\/ unpacked array of 8 32-bit vectors\nint busB [1:0];               \/\/ unpacked array of 2 integers\nbusB = busA[7:6];             \/\/ select a 2-vector slice from busA\nbusB = busA[6+:2];            \/\/ equivalent to busA[7:6]; typo fixed, thanks Tomer!\n<\/pre>\n\n\n\n<h3 class=\"wp-block-heading\">Assignments, Copying, and other Operations<\/h3>\n\n\n\n<p>SystemVerilog arrays support many more operations than Verilog arrays. The following operations can be performed on both packed and unpacked arrays.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted lang:default decode:true\">A       = B;       \/\/ reading and writing the array\nA[i:j]  = B[i:j];  \/\/ reading and writing a slice of the array\nA[x+:c] = B[y+:d]; \/\/ reading and writing a variable slice of the array\nA[i]    = B[i];    \/\/ accessing an element of the array\nA       == B;      \/\/ equality operations on the array\nA[i:j]  != B[i:j]; \/\/ equality operations on slice of the array\n<\/pre>\n\n\n\n<h3 class=\"wp-block-heading\">Packed Array Assignment<\/h3>\n\n\n\n<p>A SystemVerilog packed array can be assigned at once like a multi-bit vector, or also as an individual element or slice, and more.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted lang:default decode:true\">logic [1:0][1:0][7:0] packed_3d_array;\n\nalways_ff @(posedge clk, negedge rst_n)\n  if (!rst_n) begin\n    packed_3d_array &lt;= '0;      \/\/ assign 0 to all elements of array\n  end\n  else begin\n    packed_3d_array[0][0][0]   &lt;= 1'b0;         \/\/ assign one bit\n    packed_3d_array[0][0]      &lt;= 8'h0a;        \/\/ assign one element\n    packed_3d_array[0][0][3:0] &lt;= 4'ha;         \/\/ assign part select\n    packed_3d_array[0]         &lt;= 16'habcd;     \/\/ assign slice\n    packed_3d_array            &lt;= 32'h01234567; \/\/ assign entire array as vector\n  end\n<\/pre>\n\n\n\n<script async=\"\" src=\"https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811\" crossorigin=\"anonymous\"><\/script>\n<ins class=\"adsbygoogle\" style=\"display:block; text-align:center;\" data-ad-layout=\"in-article\" data-ad-format=\"fluid\" data-ad-client=\"ca-pub-9720137902431811\" data-ad-slot=\"7477548078\"><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n\n\n\n<h3 class=\"wp-block-heading\">Unpacked Array Assignment<\/h3>\n\n\n\n<p>All or multiple elements of a SystemVerilog unpacked array can be assigned at once to a list of values. The list can contain values for individual array elements, or a default value for the entire array.<\/p>\n\n\n\n<pre class=\"wp-block-preformatted lang:default decode:true\">logic [7:0] a, b, c;\nlogic [7:0] d_array[0:3];\nlogic [7:0] e_array[3:0]; \/\/ note index of unpacked dimension is reversed\n                          \/\/ personally, I prefer this form\nlogic [7:0] mult_array_a[3:0][3:0];\nlogic [7:0] mult_array_b[3:0][3:0];\n\nalways_ff @(posedge clk, negedge rst_n)\n  if (!rst_n) begin\n    d_array &lt;= '{default:0};      \/\/ assign 0 to all elements of array\n  end\n  else begin\n    d_array        &lt;= '{8'h00, c, b, a}; \/\/ d_array[0]=8'h00, d_array[1]=c, d_array[2]=b, d_array[3]=a\n    e_array        &lt;= '{8'h00, c, b, a}; \/\/ e_array[3]=8'h00, e_array[2]=c, e_array[1]=b, d_array[0]=a\n    mult_array_a   &lt;= '{'{8'h00, 8'h01, 8'h02, 8'h03},\n                        '{8'h04, 8'h05, 8'h06, 8'h07},\n                        '{8'h08, 8'h09, 8'h0a, 8'h0b},\n                        '{8'h0c, 8'h0d, 8'h0e, 8'h0f}}; \/\/ assign to full array\n    mult_array_b[3] &lt;= '{8'h00, 8'h01, 8'h02, 8'h03}; \/\/ assign to slice of array\n  end\n<\/pre>\n\n\n\n<h2 class=\"wp-block-heading\">Conclusion<\/h2>\n\n\n\n<p>This article described the two new types of SystemVerilog arrays&#8212;<em>packed<\/em> and <em>unpacked<\/em>&#8212;as well as the many new features that can be used to manipulate SystemVerilog arrays. The features described in this article are all synthesizable, so you can safely use them in SystemVerilog based RTL designs to simplify coding. In the next part of the SystemVerilog arrays article, I will discuss more usages of SystemVerilog arrays that can make your SystemVerilog design code even more efficient. Stay tuned!<\/p>\n\n\n\n<h2 class=\"wp-block-heading\">Resources<\/h2>\n\n\n\n<ul><li><a href=\"http:\/\/sutherland-hdl.com\/papers\/2013-SNUG-SV_Synthesizable-SystemVerilog_paper.pdf\">Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification<\/a><\/li><li>1888-2012 IEEE Standard for SystemVerilog<\/li><li><a href=\"http:\/\/buy.geni.us\/Proxy.ashx?TSID=17139&amp;GR_URL=https%3A%2F%2Fwww.amazon.com%2FSystemVerilog-Design-Second-Hardware-Modeling%2Fdp%2F0387333991%3FSubscriptionId%3DAKIAJ6LKBSG7CEXF2BFQ%26tag%3Dverpro08us-20%26linkCode%3Dxm2%26camp%3D2025%26creative%3D165953%26creativeASIN%3D0387333991\">SystemVerilog for Design Second Edition:<br>A Guide to Using SystemVerilog for Hardware Design and Modeling<\/a><\/li><\/ul>\n\n\n\n<h2 class=\"wp-block-heading\">Sample Source Code<\/h2>\n\n\n\n<p>The accompany source code for this article is a toy example module and testbench that illustrates SystemVerilog array capabilities, including using an array as a port, assigning multi-dimensional arrays, and assigning slices of arrays. Download and run it to see how it works!<\/p>\n\n\n\n<p>[lab_subscriber_download_form download_id=11].<\/p>\n\n\n\n\n\n\n<script async src=\"https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811\"\n     crossorigin=\"anonymous\"><\/script>\n<ins class=\"adsbygoogle\"\n     style=\"display:block\"\n     data-ad-format=\"autorelaxed\"\n     data-ad-client=\"ca-pub-9720137902431811\"\n     data-ad-slot=\"3587260091\"><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n","protected":false},"excerpt":{"rendered":"<p>In my last article on plain old Verilog Arrays, I discussed their very limited feature set. In comparison, SystemVerilog arrays have greatly expanded capabilities both for writing synthesizable RTL, and for writing non-synthesizable test benches. In this article, we&#8217;ll take a look at the synthesizable features of SystemVerilog Arrays we can use when writing design &#8230; <a title=\"SystemVerilog Arrays, Flexible and Synthesizable\" class=\"read-more\" href=\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/\" aria-label=\"More on SystemVerilog Arrays, Flexible and Synthesizable\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"jetpack_post_was_ever_published":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"footnotes":"","_jetpack_memberships_contains_paid_content":false,"jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":true,"jetpack_social_options":{"image_generator_settings":{"template":"highway","enabled":false}}},"categories":[13],"tags":[33],"jetpack_publicize_connections":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v22.6 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>SystemVerilog Arrays, Flexible and Synthesizable - Verilog Pro<\/title>\n<meta name=\"description\" content=\"SystemVerilog arrays have greatly expanded features compared to Verilog arrays. This article describes the synthesizable features of SystemVerilog Arrays.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"SystemVerilog Arrays, Flexible and Synthesizable - Verilog Pro\" \/>\n<meta property=\"og:description\" content=\"SystemVerilog arrays have greatly expanded features compared to Verilog arrays. This article describes the synthesizable features of SystemVerilog Arrays.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/\" \/>\n<meta property=\"og:site_name\" content=\"Verilog Pro\" \/>\n<meta property=\"article:published_time\" content=\"2017-10-10T17:00:44+00:00\" \/>\n<meta property=\"article:modified_time\" content=\"2022-06-26T07:08:33+00:00\" \/>\n<meta property=\"og:image\" content=\"http:\/\/www.verilogpro.com\/wp-content\/uploads\/2015\/09\/VLSIDesign-thumbnail.png\" \/>\n<meta name=\"author\" content=\"Jason Yu\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:creator\" content=\"@jasonkky\" \/>\n<meta name=\"twitter:site\" content=\"@jasonkky\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Jason Yu\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"5 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/\"},\"author\":{\"name\":\"Jason Yu\",\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af\"},\"headline\":\"SystemVerilog Arrays, Flexible and Synthesizable\",\"datePublished\":\"2017-10-10T17:00:44+00:00\",\"dateModified\":\"2022-06-26T07:08:33+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/\"},\"wordCount\":693,\"commentCount\":36,\"publisher\":{\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af\"},\"keywords\":[\"array\"],\"articleSection\":[\"SystemVerilog\"],\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/#respond\"]}]},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/\",\"url\":\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/\",\"name\":\"SystemVerilog Arrays, Flexible and Synthesizable - Verilog Pro\",\"isPartOf\":{\"@id\":\"https:\/\/www.verilogpro.com\/#website\"},\"datePublished\":\"2017-10-10T17:00:44+00:00\",\"dateModified\":\"2022-06-26T07:08:33+00:00\",\"description\":\"SystemVerilog arrays have greatly expanded features compared to Verilog arrays. This article describes the synthesizable features of SystemVerilog Arrays.\",\"breadcrumb\":{\"@id\":\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/www.verilogpro.com\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"SystemVerilog Arrays, Flexible and Synthesizable\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.verilogpro.com\/#website\",\"url\":\"https:\/\/www.verilogpro.com\/\",\"name\":\"Verilog Pro\",\"description\":\"Verilog and Systemverilog Resources for Design and Verification\",\"publisher\":{\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.verilogpro.com\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"en-US\"},{\"@type\":[\"Person\",\"Organization\"],\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af\",\"name\":\"Jason Yu\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/\",\"url\":\"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g\",\"contentUrl\":\"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g\",\"caption\":\"Jason Yu\"},\"logo\":{\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/\"},\"description\":\"Jason has 14 years' experience in the semiconductor industry, designing and verifying Solid State Drive controller SoC. His areas of work include microarchitecture and RTL design, dynamic and formal verification using UVM and Cadence JasperGold, and full-chip low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in any way.\",\"sameAs\":[\"http:\/\/www.verilogpro.com\",\"https:\/\/ca.linkedin.com\/in\/jasonkky\",\"https:\/\/x.com\/jasonkky\"],\"url\":\"https:\/\/www.verilogpro.com\/author\/jasonkkygmail-com\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"SystemVerilog Arrays, Flexible and Synthesizable - Verilog Pro","description":"SystemVerilog arrays have greatly expanded features compared to Verilog arrays. This article describes the synthesizable features of SystemVerilog Arrays.","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/","og_locale":"en_US","og_type":"article","og_title":"SystemVerilog Arrays, Flexible and Synthesizable - Verilog Pro","og_description":"SystemVerilog arrays have greatly expanded features compared to Verilog arrays. This article describes the synthesizable features of SystemVerilog Arrays.","og_url":"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/","og_site_name":"Verilog Pro","article_published_time":"2017-10-10T17:00:44+00:00","article_modified_time":"2022-06-26T07:08:33+00:00","og_image":[{"url":"http:\/\/www.verilogpro.com\/wp-content\/uploads\/2015\/09\/VLSIDesign-thumbnail.png"}],"author":"Jason Yu","twitter_card":"summary_large_image","twitter_creator":"@jasonkky","twitter_site":"@jasonkky","twitter_misc":{"Written by":"Jason Yu","Est. reading time":"5 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"Article","@id":"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/#article","isPartOf":{"@id":"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/"},"author":{"name":"Jason Yu","@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af"},"headline":"SystemVerilog Arrays, Flexible and Synthesizable","datePublished":"2017-10-10T17:00:44+00:00","dateModified":"2022-06-26T07:08:33+00:00","mainEntityOfPage":{"@id":"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/"},"wordCount":693,"commentCount":36,"publisher":{"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af"},"keywords":["array"],"articleSection":["SystemVerilog"],"inLanguage":"en-US","potentialAction":[{"@type":"CommentAction","name":"Comment","target":["https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/#respond"]}]},{"@type":"WebPage","@id":"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/","url":"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/","name":"SystemVerilog Arrays, Flexible and Synthesizable - Verilog Pro","isPartOf":{"@id":"https:\/\/www.verilogpro.com\/#website"},"datePublished":"2017-10-10T17:00:44+00:00","dateModified":"2022-06-26T07:08:33+00:00","description":"SystemVerilog arrays have greatly expanded features compared to Verilog arrays. This article describes the synthesizable features of SystemVerilog Arrays.","breadcrumb":{"@id":"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.verilogpro.com\/"},{"@type":"ListItem","position":2,"name":"SystemVerilog Arrays, Flexible and Synthesizable"}]},{"@type":"WebSite","@id":"https:\/\/www.verilogpro.com\/#website","url":"https:\/\/www.verilogpro.com\/","name":"Verilog Pro","description":"Verilog and Systemverilog Resources for Design and Verification","publisher":{"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.verilogpro.com\/?s={search_term_string}"},"query-input":"required name=search_term_string"}],"inLanguage":"en-US"},{"@type":["Person","Organization"],"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af","name":"Jason Yu","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/","url":"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g","caption":"Jason Yu"},"logo":{"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/"},"description":"Jason has 14 years' experience in the semiconductor industry, designing and verifying Solid State Drive controller SoC. His areas of work include microarchitecture and RTL design, dynamic and formal verification using UVM and Cadence JasperGold, and full-chip low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in any way.","sameAs":["http:\/\/www.verilogpro.com","https:\/\/ca.linkedin.com\/in\/jasonkky","https:\/\/x.com\/jasonkky"],"url":"https:\/\/www.verilogpro.com\/author\/jasonkkygmail-com\/"}]}},"jetpack_featured_media_url":"","jetpack_sharing_enabled":true,"jetpack_shortlink":"https:\/\/wp.me\/p6Du8T-9N","jetpack-related-posts":[],"_links":{"self":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/posts\/607"}],"collection":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/comments?post=607"}],"version-history":[{"count":19,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/posts\/607\/revisions"}],"predecessor-version":[{"id":822,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/posts\/607\/revisions\/822"}],"wp:attachment":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/media?parent=607"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/categories?post=607"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/tags?post=607"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}