{"id":598,"date":"2017-07-25T10:00:47","date_gmt":"2017-07-25T17:00:47","guid":{"rendered":"http:\/\/www.verilogpro.com\/?p=598"},"modified":"2022-06-27T00:39:14","modified_gmt":"2022-06-27T07:39:14","slug":"verilog-arrays-plain-simple","status":"publish","type":"post","link":"https:\/\/www.verilogpro.com\/verilog-arrays-plain-simple\/","title":{"rendered":"Verilog Arrays Plain and Simple"},"content":{"rendered":"\n

Arrays are an integral part of many modern programming languages. Verilog arrays are quite simple; the Verilog-2005 standard has only 2 pages describing arrays, a stark contrast from SystemVerilog-2012 which has 20+ pages on arrays. Having a good understanding of what array features are available in plain Verilog will help understand the motivation and improvements introduced in SystemVerilog. In this article I will restrict the discussion to plain Verilog arrays, and discuss SystemVerilog arrays in an upcoming post.<\/p>\n\n\n\n

Verilog Arrays<\/h2>\n\n\n\n

Verilog arrays can be used to group elements into multidimensional objects to be manipulated more easily. Since Verilog does not have user-defined types, we are restricted to arrays of built-in Verilog types like nets, regs, and other Verilog variable types.<\/p>\n\n\n\n

Each array dimension is declared by having the min and max indices in square brackets. Array indices can be written in either direction:<\/p>\n\n\n\n

array_name[least_significant_index:most_significant_index], e.g. array1[0:7]\narray_name[most_significant_index:least_significant_index], e.g. array2[7:0]<\/code><\/code><\/pre>\n\n\n\n
Personally I prefer the array2<\/em> form for consistency, since I also write vector indices (square brackets before the array name) in [most_significant:least_significant] form. However, this is only a preference not a requirement.<\/p>\n\n\n\n
A multi-dimensional array can be declared by having multiple dimensions after<\/em> the array declaration. Any square brackets before<\/em> the array identifier is part of the data type that is being replicated in the array.<\/p>\n\n\n\n
The Verilog-2005 specification also calls a one-dimensional array with elements of type reg<\/b> a memory<\/i>. It is useful for modeling memory elements like read-only memory (ROM), and random access memory (RAM).<\/p>\n\n\n\n
Verilog arrays are synthesizable, so you can use them in synthesizable RTL code.<\/p>\n\n\n\n
reg [31:0] x[127:0];          \/\/ 128-element array of 32-bit wide reg\nwire[15:0] y[  7:0], z[7:0];  \/\/ 2 arrays of 16-bit wide wires indexed from 7 to 0\nreg [ 7:0] mema   [255:0];    \/\/ 256-entry memory mema of 8-bit registers\nreg        arrayb [  7:0][255:0]; \/\/ two-dimensional array of one bit registers<\/code><\/pre>\n\n\n\n