{"id":499,"date":"2017-05-02T10:00:40","date_gmt":"2017-05-02T17:00:40","guid":{"rendered":"http:\/\/www.verilogpro.com\/?p=499"},"modified":"2022-06-26T00:10:29","modified_gmt":"2022-06-26T07:10:29","slug":"verilog-reg-verilog-wire-systemverilog-logic","status":"publish","type":"post","link":"https:\/\/www.verilogpro.com\/verilog-reg-verilog-wire-systemverilog-logic\/","title":{"rendered":"Verilog reg, Verilog wire, SystemVerilog logic. What’s the difference?"},"content":{"rendered":"\n
The difference between Verilog reg<\/strong> and Verilog wire<\/strong> frequently confuses many programmers just starting with the language (certainly confused me!). As a beginner, I was told to follow these guidelines, which seemed to generally work:<\/p>\n\n\n\n Then when I adopted SystemVerilog for writing RTL designs, I was told everything can now be “type logic”. That again generally worked, but every now and then I would run into a cryptic error message about variables, nets, and assignment.<\/p>\n\n\n\n So I decided to find out exactly how these data types worked to write this article. I dug into the language reference manual, searched for the now-defunct Verilog-2005 standard document, and got into a bit of history lesson. Read on for my discovery of the differences between Verilog reg<\/b>, Verilog wire<\/b>, and SystemVerilog logic<\/b>.<\/p>\n\n\n\n Verilog data types are divided into two main groups: nets and variables. The distinction comes from how they are intended to represent different hardware structures. <\/p>\n\n\n\n A net data type represents a physical connection between structural entities (think a plain wire), such as between gates or between modules. It does not store any value. Its value is derived from what is being driven from its driver(s). Verilog wire<\/b> is probably the most common net data type, although there are many other net data types such as tri<\/b>, wand<\/b>, supply0<\/b>. <\/p>\n\n\n\n A variable data type generally represents a piece of storage. It holds a value assigned to it until the next assignment. Verilog reg<\/b> is probably the most common variable data type. Verilog reg<\/b> is generally used to model hardware registers (although it can also represent combinatorial logic, like inside an always@(*)<\/b> block). Other variable data types include integer<\/b>, time<\/strong>, real<\/strong>, realtime<\/strong>. <\/p>\n\n\n\n Almost all Verilog data types are 4-state, which means they can take on 4 values: <\/p>\n\n\n\n Verilog rule of thumb 1<\/strong>: use Verilog reg<\/strong> when you want to represent a piece of storage, and use Verilog wire<\/strong> when you want to represent a physical connection.<\/p>\n<\/div><\/div><\/div>\n\n\n\nVerilog data types, Verilog reg, Verilog wire<\/h2>\n\n\n\n