{"id":45,"date":"2015-08-30T08:19:49","date_gmt":"2015-08-30T08:19:49","guid":{"rendered":"http:\/\/www.verilogpro.com\/?p=45"},"modified":"2022-06-27T00:43:57","modified_gmt":"2022-06-27T07:43:57","slug":"x-propagation-with-vcs-xprop","status":"publish","type":"post","link":"https:\/\/www.verilogpro.com\/x-propagation-with-vcs-xprop\/","title":{"rendered":"SystemVerilog and Verilog X Optimism – Hardware-like X Propagation with Xprop"},"content":{"rendered":"\n

In part 2 of this series, SystemVerilog and Verilog X Optimism – What About X Pessimism?<\/a>, I discussed several coding styles that help to reduce the risk of missing design bugs due to Verilog X optimism. In part 3, we will take a look at how proprietary simulator features help avoid the problem by smartly doing X propagation. Specifically, we will look at Synopsys VCS Xprop.<\/p>\n\n\n\n

Like the name suggests, X propagation means propagating an X at the input of some logic to its outputs. Synopsys VCS Xprop can do so smartly, in many cases avoiding X optimism, making simulation behave closer to real hardware.<\/p>\n\n\n\n

Xprop has three modes: xmerge, tmerge, and vmerge. Xmerge simply assigns X to outputs whenever any of the inputs are X. This behaviour is similar to what would be observed in gate level simulations, but can sometimes be even more pessimistic. With tmerge, when an input is X, the simulator will traverse both code paths assuming the input is 0 and 1, and compare the results. If the results are the same, the determinate result is assigned to the output. If the results differ, X is assigned to the output to do X propagation. Vermge basically disables Xprop, allowing classic Verilog X optimism.<\/p>\n\n\n\n

Consider the if…else<\/b> statement again from part 1<\/a> of the series:<\/p>\n\n\n\n

always_ff @(posedge clk) begin\n  if (cond)\n    c <= a;\n  else\n    c <= b;\nend\n<\/pre>\n\n\n\n
\"MUX21NAND<\/a><\/figure><\/div>\n\n\n\n
Let’s also add a gate level implementation of this multiplexer for comparison.
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