{"id":280,"date":"2016-03-28T10:00:47","date_gmt":"2016-03-28T17:00:47","guid":{"rendered":"http:\/\/www.verilogpro.com\/?p=280"},"modified":"2022-09-29T00:40:06","modified_gmt":"2022-09-29T07:40:06","slug":"clock-domain-crossing-part-1","status":"publish","type":"post","link":"https:\/\/www.verilogpro.com\/clock-domain-crossing-part-1\/","title":{"rendered":"Clock Domain Crossing Design &#8211; 3 Part Series"},"content":{"rendered":"\n<p>Thank you for all your interest in my last post on <a href='http:\/\/www.verilogpro.com\/asynchronous-fifo-design\/'>Dual-Clock Asynchronous FIFO in SystemVerilog<\/a>! I decided to continue the theme of clock domain crossing (CDC) design techniques, and look at several other methods for passing control signals and data between asynchronous clock domains. This is perfect timing because I&#8217;m just about to create a new revision of one of my design blocks at work, which incorporates many of these concepts. I, too, can use a refresher \ud83d\ude42<\/p>\n\n\n\n<p>The concepts in this article are mostly taken from Cliff Cumming's very comprehensive paper <a href='http:\/\/www.sunburst-design.com%2Fpapers%2FCummingsSNUG2008Boston_CDC.pdf'>Clock Domain Crossing (CDC) Design &amp; Verification Techniques Using SystemVerilog<\/a>. I&#8217;ve broken the topics into 3 parts:<\/p>\n\n\n\n<ul><li>Part 1 &#8211; metastability and challenges with passing single bit signals across a clock domain crossing (CDC), and single-bit synchronizer<\/li><li><a href='http:\/\/www.verilogpro.com\/clock-domain-crossing-part-2\/'>Part 2<\/a> &#8211; challenges with passing multi-bit signals across a CDC, and multi-bit synchronizer<\/li><li><a href='http:\/\/www.verilogpro.com\/clock-domain-crossing-design-part-3\/'>Part 3<\/a> &#8211; design of a complete multi-bit synchronizer with feedback acknowledge<\/li><\/ul>\n\n\n\n<p>Let&#8217;s get right to it!<\/p>\n\n\n\n<h2 class='wp-block-heading'>What is Metastability?<\/h2>\n\n\n\n<p>Any discussion of clock domain crossing (CDC) should start with a basic understanding of metastability and synchronization. In layman&#8217;s terms, metastability refers to an unstable intermediate state, where the slightest disturbance will cause a resolution to a stable state. When applied to flip-flops in digital circuits, it means a state where the flip-flop&#8217;s output may not have settled to the final expected value.<\/p>\n\n\n\n<p>One of the ways a flip-flop can enter a metastable state is if its setup or hold time is violated. In an asynchronous clock domain crossing (CDC), where the source and destination clocks have no frequency relationship, a signal from the source domain has a non-zero probability of changing within the setup or hold time of a destination flip-flop it drives. Synchronization failure occurs when the output of the destination flip-flop goes metastable and does not converge to a legal state by the time its output must be sampled again (by the next flip-flop in the destination domain). Worse yet, that next flip-flop may also go metastable, causing metastability to propagate through the design!<\/p>\n\n\n\n<script async='' src='https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811' crossorigin='anonymous'><\/script>\n<ins class='adsbygoogle' style='display:block; text-align:center;' data-ad-layout='in-article' data-ad-format='fluid' data-ad-client='ca-pub-9720137902431811' data-ad-slot='7477548078'><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n\n\n\n<h2 class='wp-block-heading'>Synchronizers for Clock Domain Crossing (CDC)<\/h2>\n\n\n\n<p>A synchronizer is a circuit whose purpose is to minimize the probability of a synchronization failure. We want the metastability to resolve within a synchronization period (a period of the destination clock) so that we can safely sample the output of the flip-flop in the destination clock domain. It is possible to calculate the failure rate of a synchronizer, and this is called the <i>mean time between failure (MTBF)<\/i>.<\/p>\n\n\n\n<p>Without going into the math, the takeaway is that the probability of hitting a metastable state in a clock domain crossing (CDC) is proportional to:<\/p>\n\n\n\n<ol><li>Frequency of the destination domain<\/li><li>Rate of data crossing the clock boundary<\/li><\/ol>\n\n\n\n<p>This result gives us some ideas on how to design a good synchronizer. Interested readers can refer to <a href='http:\/\/webee.technion.ac.il\/~ran\/papers\/Metastability-and-Synchronizers.IEEEDToct2011.pdf'>Metastability and Synchronizers: A Tutorial<\/a> for a tutorial on the topic of metastability, and some interesting graphs of how flip-flops can become metastable.<\/p>\n\n\n\n<h3 class='wp-block-heading'>Two flip-flop synchronizer<\/h3>\n\n\n\n<div class='wp-block-image'><figure class='aligncenter'><a href='https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2016\/03\/2ff_sync.png' rel='attachment wp-att-295'><img src='https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2016\/03\/2ff_sync.png?w=1200' alt='Two flip-flop synchronizer for clock domain crossing (CDC)' class='wp-image-295' data-recalc-dims=\"1\"\/><\/a><\/figure><\/div>\n\n\n\n<p>The most basic synchronizer is two flip-flop in series, both clocked by the destination clock. This simple and unassuming circuit is called a <i>two flip-flop synchronizer<\/i>. If the input data changes very close to the receiving clock edge (within setup\/hold time), the first flip-flop in the synchronizer may go metastable, but there is still a full clock for the signal to become stable before being sampled by the second flip-flop. The destination domain logic then uses the output from the second flip-flop. Theoretically it is possible for the signal to still be metastable by the time it is clocked into the second flip-flop (every MTBF years). In that case a synchronization failure occurs and the design would likely malfunction.<\/p>\n\n\n\n<p>The two flip-flop synchronizer is sufficient for many applications. Very high speed designs may require a three flip-flop synchronizer to give sufficient MTBF. To further increase MTBF, two flip-flop synchronizers are sometimes built from fast library cells (low threshold voltage) that have better setup\/hold time characteristics.<\/p>\n\n\n\n<h3 class='wp-block-heading'>Registering source signals into the synchronizer<\/h3>\n\n\n\n<p>It is a generally good practice to register signals in the source clock domain before sending them across the clock domain crossing (CDC) into synchronizers. This eliminates combinational glitches, which can effectively increase the rate of data crossing the clock boundary, reducing MTBF of the synchronizer.<\/p>\n\n\n\n<h2 class='wp-block-heading'>Synchronizing Slow Signals Into Fast Clock Domain<\/h2>\n\n\n\n<p>The easy case is passing signals from a slow clock domain to a fast clock domain. This is generally not a problem as long as the faster clock is &gt; 1.5x frequency of the slow clock. The fast destination clock will simply sample the slow signal more than once. In these cases, a simple two-flip-flop synchronizer may suffice.<\/p>\n\n\n\n<p>If the fast clock is &lt; 1.5x frequency of the slow clock, then there can be a potential problem, and you should use one of the solutions in the next section.<\/p>\n\n\n\n<h2 class='wp-block-heading'>Synchronizing Fast Signals Into Slow Clock Domain<\/h2>\n\n\n\n<p>The more difficult case is, of course, passing a fast signal into a slow clock domain. The obvious problem is if a pulse on the fast signal is shorter than the period of the slow clock, then the pulse can disappear before being sampled by the slow clock. This scenario is shown in the waveform below.<\/p>\n\n\n\n<div class='wp-block-image'><figure class='aligncenter'><a href='https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2016\/03\/fastsrc_pulse2.png' rel='attachment wp-att-299'><img src='https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2016\/03\/fastsrc_pulse2.png?w=1200' alt='Fast source pulse missed by slow clock in clock domain crossing (CDC)' class='wp-image-299' data-recalc-dims=\"1\"\/><\/a><\/figure><\/div>\n\n\n\n<p>A less obvious problem is even if the pulse was just slightly wider than the period of the slow clock, the signal can change within the setup\/hold time of the destination flip-flop (on the slow clock), violating timing and causing metastability.<\/p>\n\n\n\n<p>Before deciding on how to handle this clock domain crossing (CDC), you should first ask yourself whether every value of the source signal is needed in the destination domain. If you don&#8217;t (meaning it is okay to drop some values) then it may suffice to use an &#8220;open-loop&#8221; synchronizer without acknowledgement. An example is the gray code pointer from my <a href='http:\/\/www.verilogpro.com\/asynchronous-fifo-design\/'>Dual-Clock Asynchronous FIFO in SystemVerilog<\/a>; it needs to be accurate when read, but the FIFO pointer may advance several times before a read occurs and the value is used. If, on the other hand, you need every value in the destination domain, then a &#8220;closed-loop&#8221; synchronizer with acknowledgement may be needed.<\/p>\n\n\n\n<script async='' src='https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811' crossorigin='anonymous'><\/script>\n<ins class='adsbygoogle' style='display:block; text-align:center;' data-ad-layout='in-article' data-ad-format='fluid' data-ad-client='ca-pub-9720137902431811' data-ad-slot='7477548078'><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n\n\n\n<h3 class='wp-block-heading'>Single bit &#8212; two flip-flop synchronizer<\/h3>\n\n\n\n<p>A simple two flip-flop synchronizer is the fastest way to pass signals across a clock domain crossing. It can be sufficient in many applications, as long as the signal generated in the fast clock domain is wider than the cycle time of the slow clock. For example, if you just need to synchronize a slow changing status signal, this may work. A safe rule of thumb is the signal must be wider than 1.5x the cycle width of the destination clock (&#8220;three receiving clock edge&#8221; requirement coined in Mark Litterick&#8217;s <a href='http:\/\/www.verilab.com\/files\/sva_cdc_paper_dvcon2006.pdf'>paper on clock domain crossing verification<\/a>). This guarantees the signal will be sampled by at least one (but maybe more) clock edge of the destination clock. The requirement can be easily checked using SystemVerilog Assertions (SVA).<\/p>\n\n\n\n<p>The 1.5x cycle width is easy to enforce when the relative clock frequencies of the source and destination are fixed. But there are real world scenarios where they won&#8217;t be. In a memory controller design I worked on, the destination clock can take on three different frequencies, which can be either faster\/slower\/same as the source clock. In that situation, it was not easy to design the clock domain crossing signals to meet the 1.5x cycle width of the slowest destination clock.<\/p>\n\n\n\n<h3 class='wp-block-heading'>Single bit &#8212; synchronizer with feedback acknowledge<\/h3>\n\n\n\n<p>A synchronizer with feedback acknowledge is slightly more involved, but not much. The figure below illustrates how it works.<\/p>\n\n\n\n<div class='wp-block-image'><figure class='aligncenter'><a href='https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2016\/03\/1sig_feedback_sync.png' rel='attachment wp-att-301'><img src='https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2016\/03\/1sig_feedback_sync.png?w=1200' alt='Single bit feedback synchronizer for clock domain crossing (CDC) diagram ' class='wp-image-301' data-recalc-dims=\"1\"\/><\/a><\/figure><\/div>\n\n\n\n<p>The source domain sends the signal to the destination clock domain through a two flip-flop synchronizer, then passes the synchronized signal back to the source clock domain through another two flip-flop synchronizer as a feedback acknowledgement. The figure below shows a waveform of the synchronizer.<\/p>\n\n\n\n<div class='wp-block-image'><figure class='aligncenter'><a href='https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2016\/03\/1sig_feedback_sync_wave.png' rel='attachment wp-att-302'><img src='https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2016\/03\/1sig_feedback_sync_wave.png?w=1200' alt='Single bit feedback synchronizer for clock domain crossing (CDC) waveform' class='wp-image-302' data-recalc-dims=\"1\"\/><\/a><\/figure><\/div>\n\n\n\n<p>This solution is very safe, but it does come at a cost of increased delay due to synchronizing in both directions before allowing the signal to change again. This solution would work in my memory controller design to handle the varying clock frequency relationship.<\/p>\n\n\n\n<h2 class='wp-block-heading'>Conclusion<\/h2>\n\n\n\n<p>Even though we would all like to live in a purely synchronous world, in real world applications you will undoubtedly run into designs that require multiple asynchronous clocks. This article described two basic techniques to pass a single control signal across a clock domain crossing (CDC). Clock domain crossing (CDC) logic bugs are elusive and extremely difficult to debug, so it is imperative to design synchronization logic correctly from the start!<\/p>\n\n\n\n<p>Passing a single control signal across a clock domain crossing (CDC) isn&#8217;t very exciting. In <a href='http:\/\/www.verilogpro.com\/clock-domain-crossing-part-2\/'>Clock Domain Crossing Techniques &#8211; Part 2<\/a>, I will discuss the difficulties with passing multiple control signals, and some possible solutions.<\/p>\n\n\n\n<h2 class='wp-block-heading'>References<\/h2>\n\n\n\n<ul><li><a href='http:\/\/webee.technion.ac.il\/~ran\/papers\/Metastability-and-Synchronizers.IEEEDToct2011.pdf'>Metastability and Synchronizers: A Tutorial<\/a><\/li><li><a href='http:\/\/www.sunburst-design.com\/papers\/CummingsSNUG2001SJ_AsyncClk.pdf'>Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs<\/a><\/li><li><a href='http:\/\/www.sunburst-design.com\/papers\/CummingsSNUG2008Boston_CDC.pdf'>Clock Domain Crossing (CDC) Design &amp; Verification Techniques Using SystemVerilog<\/a><\/li><li><a href='http:\/\/www.verilab.com\/files\/sva_cdc_paper_dvcon2006.pdf'>Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions<\/a><\/li><\/ul>\n\n\n\n<h2 class='wp-block-heading'>Sample Source Code<\/h2>\n\n\n\n<p>The accompany source code for this article is the <strong>single-bit feedback synchronizer and testbench<\/strong>, which generates the following waveform when run. Download and run it to see how it works!<\/p>\n\n\n\n<div class='wp-block-image'><figure class='aligncenter'><a href='https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2016\/03\/1sig_feedback_sync_sim.png' rel='attachment wp-att-304'><img src='https:\/\/i0.wp.com\/www.verilogpro.com\/wp-content\/uploads\/2016\/03\/1sig_feedback_sync_sim.png?w=1200' alt='Single bit feedback synchronizer simulation' class='wp-image-304' data-recalc-dims=\"1\"\/><\/a><\/figure><\/div>\n\n\n\n<div class=\"wpcf7 no-js\" id=\"wpcf7-f859-o1\" lang=\"en-US\" dir=\"ltr\">\n<div class=\"screen-reader-response\">\n<p role=\"status\" aria-live=\"polite\" aria-atomic=\"true\"><\/p> <ul><\/ul>\n<\/div>\n<form action=\"\/wp-json\/wp\/v2\/posts\/280#wpcf7-f859-o1\" method=\"post\" class=\"wpcf7-form init\" aria-label=\"Contact form\" novalidate=\"novalidate\" data-status=\"init\">\n<label class=\"ebd_input\"><input type=\"hidden\" name=\"ebd_downloads[]\" value=\"363|single_bit_feedback_synchronizer_tb.zip\"> <\/label><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"title|single_bit_feedback_synchronizer_tb.zip\"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"checked|no\"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"hide_form|yes\"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"radio|no\"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"from_name| \"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"file_thumbnail|no\"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"item_id|4\"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"form_id|wpcf7-f859-o1\"><div style=\"display: none;\">\n<input type=\"hidden\" name=\"_wpcf7\" value=\"859\">\n<input type=\"hidden\" name=\"_wpcf7_version\" value=\"5.7.6\">\n<input type=\"hidden\" name=\"_wpcf7_locale\" value=\"en_US\">\n<input type=\"hidden\" name=\"_wpcf7_unit_tag\" value=\"wpcf7-f859-o1\">\n<input type=\"hidden\" name=\"_wpcf7_container_post\" value=\"0\">\n<input type=\"hidden\" name=\"_wpcf7_posted_data_hash\" value=\"\">\n<input type=\"hidden\" name=\"_wpcf7_recaptcha_response\" value=\"\">\n<\/div>\n<p><label> Your Name (required)<br>\n<span class=\"wpcf7-form-control-wrap\" data-name=\"your-name\"><input size=\"40\" class=\"wpcf7-form-control wpcf7-text wpcf7-validates-as-required\" aria-required=\"true\" aria-invalid=\"false\" value=\"\" type=\"text\" name=\"your-name\"><\/span> <\/label>\n<\/p>\n<p><label> Your Email (required)<br>\n<span class=\"wpcf7-form-control-wrap\" data-name=\"your-email\"><input size=\"40\" class=\"wpcf7-form-control wpcf7-text wpcf7-email wpcf7-validates-as-required wpcf7-validates-as-email\" aria-required=\"true\" aria-invalid=\"false\" value=\"\" type=\"email\" name=\"your-email\"><\/span> <\/label>\n<\/p>\n<p>Answer <span class=\"wpcf7-form-control-wrap\" data-name=\"random-math-quiz\"><label><span class=\"wpcf7-quiz-label\">2+7<\/span> <input size=\"40\" class=\"wpcf7-form-control wpcf7-quiz\" autocomplete=\"off\" aria-required=\"true\" aria-invalid=\"false\" type=\"text\" name=\"random-math-quiz\"><\/label><input type=\"hidden\" name=\"_wpcf7_quiz_answer_random-math-quiz\" value=\"dcb4a243ede50c57c5dcf51852e0977d\"><\/span>\n<\/p>\n<p><input class=\"wpcf7-form-control has-spinner wpcf7-submit\" type=\"submit\" value=\"Send me the source code!\">\n<\/p>\n<p style=\"display: none !important;\" class=\"akismet-fields-container\" data-prefix=\"_wpcf7_ak_\"><label>&Delta;<textarea name=\"_wpcf7_ak_hp_textarea\" cols=\"45\" rows=\"8\" maxlength=\"100\"><\/textarea><\/label><input type=\"hidden\" id=\"ak_js_1\" name=\"_wpcf7_ak_js\" value=\"174\"><script>document.getElementById( \"ak_js_1\" ).setAttribute( \"value\", ( new Date() ).getTime() );<\/script><\/p>\n<div class=\"wpcf7-response-output\" aria-hidden=\"true\"><\/div>\n<script> var wpcf7f859o1selectors = \"div#wpcf7-f859-o1 > form > .ebd_input > input\";\n        \n        jQuery( wpcf7f859o1selectors ).on( \"click\", function () {\n            var wpcf7f859o1n = jQuery( wpcf7f859o1selectors+\":checked\" ).length;\n            \n            if(wpcf7f859o1n > 0) jQuery(\"div#wpcf7-f859-o1 form \").children().not('.ebd_input').not('.wpcf7-response-output').not('script').show();\n            else jQuery(\"div#wpcf7-f859-o1 form \").children().not('.ebd_input').not('.wpcf7-response-output').not('script').hide();\n        } );    jQuery('.wpcf7-response-output').hide();\n<\/script>\n<\/form>\n<\/div>\n\n\n\n\n\n\n\n<script async='' src='https:\/\/pagead2.googlesyndication.com\/pagead\/js\/adsbygoogle.js?client=ca-pub-9720137902431811' crossorigin='anonymous'><\/script>\n<ins class='adsbygoogle' style='display:block' data-ad-format='autorelaxed' data-ad-client='ca-pub-9720137902431811' data-ad-slot='3587260091'><\/ins>\n<script>\n     (adsbygoogle = window.adsbygoogle || []).push({});\n<\/script>\n","protected":false},"excerpt":{"rendered":"<p>Thank you for all your interest in my last post on Dual-Clock Asynchronous FIFO in SystemVerilog! I decided to continue the theme of clock domain crossing (CDC) design techniques, and look at several other methods for passing control signals and data between asynchronous clock domains. This is perfect timing because I&#8217;m just about to create &#8230; <a title=\"Clock Domain Crossing Design &#8211; 3 Part Series\" class=\"read-more\" href=\"https:\/\/www.verilogpro.com\/clock-domain-crossing-part-1\/\" aria-label=\"More on Clock Domain Crossing Design &#8211; 3 Part Series\">Read more<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"jetpack_post_was_ever_published":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":true,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"footnotes":"","_jetpack_memberships_contains_paid_content":false,"jetpack_publicize_message":"","jetpack_publicize_feature_enabled":true,"jetpack_social_post_already_shared":true,"jetpack_social_options":{"image_generator_settings":{"template":"highway","enabled":false}}},"categories":[3],"tags":[25],"jetpack_publicize_connections":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v22.5 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Clock Domain Crossing Design - 3 Part Series - Verilog Pro<\/title>\n<meta name=\"description\" content=\"Designing Clock domain crossing (CDC) logic requires extreme care. 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