{"id":126,"date":"2015-09-19T08:07:02","date_gmt":"2015-09-19T15:07:02","guid":{"rendered":"http:\/\/www.verilogpro.com\/?p=126"},"modified":"2022-06-27T00:42:50","modified_gmt":"2022-06-27T07:42:50","slug":"systemverilog-unique-priority","status":"publish","type":"post","link":"https:\/\/www.verilogpro.com\/systemverilog-unique-priority\/","title":{"rendered":"SystemVerilog Unique And Priority – How Do I Use Them?"},"content":{"rendered":"\n

Improperly coded Verilog case<\/b> statements can frequently cause unintended synthesis optimizations or unintended latches. These problems, if not caught in pre-silicon simulations or gate level simulations, can easily lead to a non-functional chip. The new SystemVerilog unique<\/b> and priority<\/b> keywords are designed to address these coding traps. In this article, we will take a closer look at how to use these new SystemVerilog keywords in RTL coding. The reader is assumed to have knowledge of how Verilog case<\/b> statements work. Those who are not familiar can refer to my previous post “Verilog twins: case, casez, casex. Which Should I Use?<\/a>“<\/p>\n\n\n\n

The SystemVerilog unique<\/b> and priority<\/b> modifiers are placed before an if, case, casez, casex<\/b> statement, like this:<\/p>\n\n\n\n

unique if (expression)\n  statements\nelse\n  statements\n\npriority case (case_expression)\n  case_item_1: case_expression_1\n  case_item_2: case_expression_2\nendcase<\/pre>\n\n\n\n
With the if…else<\/b> statement, the SystemVerilog unique<\/b> or priority<\/b> keyword is placed only before the first if<\/b>, but affects all subsequent else if<\/b> and else<\/b> statements.<\/p>\n\n\n\n