{"id":582,"date":"2017-04-30T22:17:41","date_gmt":"2017-05-01T05:17:41","guid":{"rendered":"http:\/\/www.verilogpro.com\/?page_id=582"},"modified":"2017-04-30T22:17:41","modified_gmt":"2017-05-01T05:17:41","slug":"page-not-found","status":"publish","type":"page","link":"https:\/\/www.verilogpro.com\/page-not-found\/","title":{"rendered":"Page Not Found!"},"content":{"rendered":"<p>Oh no! It looks like nothing was found at this location.<\/p>\n<p>But don&#8217;t leave empty handed! Get my Top 4 recommended Verilog and SystemVerilog papers!<\/p>\n<p>[lab_subscriber_download_form download_id=9]<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Oh no! It looks like nothing was found at this location. But don&#8217;t leave empty handed! Get my Top 4 recommended Verilog and SystemVerilog papers! [lab_subscriber_download_form download_id=9]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"jetpack_post_was_ever_published":false,"footnotes":""},"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v22.6 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Page Not Found! - Verilog Pro<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.verilogpro.com\/page-not-found\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Page Not Found! - Verilog Pro\" \/>\n<meta property=\"og:description\" content=\"Oh no! It looks like nothing was found at this location. But don&#8217;t leave empty handed! Get my Top 4 recommended Verilog and SystemVerilog papers! [lab_subscriber_download_form download_id=9]\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.verilogpro.com\/page-not-found\/\" \/>\n<meta property=\"og:site_name\" content=\"Verilog Pro\" \/>\n<meta property=\"og:image\" content=\"http:\/\/www.verilogpro.com\/wp-content\/uploads\/2015\/09\/VLSIDesign-thumbnail.png\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:site\" content=\"@jasonkky\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.verilogpro.com\/page-not-found\/\",\"url\":\"https:\/\/www.verilogpro.com\/page-not-found\/\",\"name\":\"Page Not Found! - Verilog Pro\",\"isPartOf\":{\"@id\":\"https:\/\/www.verilogpro.com\/#website\"},\"datePublished\":\"2017-05-01T05:17:41+00:00\",\"dateModified\":\"2017-05-01T05:17:41+00:00\",\"breadcrumb\":{\"@id\":\"https:\/\/www.verilogpro.com\/page-not-found\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.verilogpro.com\/page-not-found\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.verilogpro.com\/page-not-found\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/www.verilogpro.com\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Page Not Found!\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.verilogpro.com\/#website\",\"url\":\"https:\/\/www.verilogpro.com\/\",\"name\":\"Verilog Pro\",\"description\":\"Verilog and Systemverilog Resources for Design and Verification\",\"publisher\":{\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.verilogpro.com\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"en-US\"},{\"@type\":[\"Person\",\"Organization\"],\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af\",\"name\":\"Jason Yu\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/\",\"url\":\"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g\",\"contentUrl\":\"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g\",\"caption\":\"Jason Yu\"},\"logo\":{\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/\"},\"description\":\"Jason has 14 years' experience in the semiconductor industry, designing and verifying Solid State Drive controller SoC. His areas of work include microarchitecture and RTL design, dynamic and formal verification using UVM and Cadence JasperGold, and full-chip low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in any way.\",\"sameAs\":[\"http:\/\/www.verilogpro.com\",\"https:\/\/ca.linkedin.com\/in\/jasonkky\",\"https:\/\/x.com\/jasonkky\"]}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Page Not Found! - Verilog Pro","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.verilogpro.com\/page-not-found\/","og_locale":"en_US","og_type":"article","og_title":"Page Not Found! - Verilog Pro","og_description":"Oh no! It looks like nothing was found at this location. But don&#8217;t leave empty handed! Get my Top 4 recommended Verilog and SystemVerilog papers! [lab_subscriber_download_form download_id=9]","og_url":"https:\/\/www.verilogpro.com\/page-not-found\/","og_site_name":"Verilog Pro","og_image":[{"url":"http:\/\/www.verilogpro.com\/wp-content\/uploads\/2015\/09\/VLSIDesign-thumbnail.png"}],"twitter_card":"summary_large_image","twitter_site":"@jasonkky","schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"WebPage","@id":"https:\/\/www.verilogpro.com\/page-not-found\/","url":"https:\/\/www.verilogpro.com\/page-not-found\/","name":"Page Not Found! - Verilog Pro","isPartOf":{"@id":"https:\/\/www.verilogpro.com\/#website"},"datePublished":"2017-05-01T05:17:41+00:00","dateModified":"2017-05-01T05:17:41+00:00","breadcrumb":{"@id":"https:\/\/www.verilogpro.com\/page-not-found\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.verilogpro.com\/page-not-found\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/www.verilogpro.com\/page-not-found\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.verilogpro.com\/"},{"@type":"ListItem","position":2,"name":"Page Not Found!"}]},{"@type":"WebSite","@id":"https:\/\/www.verilogpro.com\/#website","url":"https:\/\/www.verilogpro.com\/","name":"Verilog Pro","description":"Verilog and Systemverilog Resources for Design and Verification","publisher":{"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.verilogpro.com\/?s={search_term_string}"},"query-input":"required name=search_term_string"}],"inLanguage":"en-US"},{"@type":["Person","Organization"],"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af","name":"Jason Yu","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/","url":"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g","caption":"Jason Yu"},"logo":{"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/"},"description":"Jason has 14 years' experience in the semiconductor industry, designing and verifying Solid State Drive controller SoC. His areas of work include microarchitecture and RTL design, dynamic and formal verification using UVM and Cadence JasperGold, and full-chip low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in any way.","sameAs":["http:\/\/www.verilogpro.com","https:\/\/ca.linkedin.com\/in\/jasonkky","https:\/\/x.com\/jasonkky"]}]}},"jetpack_sharing_enabled":true,"jetpack_shortlink":"https:\/\/wp.me\/P6Du8T-9o","jetpack-related-posts":[],"_links":{"self":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/pages\/582"}],"collection":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/comments?post=582"}],"version-history":[{"count":3,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/pages\/582\/revisions"}],"predecessor-version":[{"id":585,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/pages\/582\/revisions\/585"}],"wp:attachment":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/media?parent=582"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}