{"id":561,"date":"2017-04-30T17:55:29","date_gmt":"2017-05-01T00:55:29","guid":{"rendered":"http:\/\/www.verilogpro.com\/?page_id=561"},"modified":"2022-09-29T00:01:02","modified_gmt":"2022-09-29T07:01:02","slug":"resources","status":"publish","type":"page","link":"https:\/\/www.verilogpro.com\/resources\/","title":{"rendered":"Resources"},"content":{"rendered":"\n<p class='has-text-align-center'>Get the top 4 Verilog and SystemVerilog papers that shaped how I code RTL today!<\/p>\n\n\n\n<h5 class='has-text-align-center wp-block-heading'>Surprising fact: only 1 paper is about state machine coding<\/h5>\n\n\n<div class=\"wpcf7 no-js\" id=\"wpcf7-f860-o1\" lang=\"en-US\" dir=\"ltr\">\n<div class=\"screen-reader-response\">\n<p role=\"status\" aria-live=\"polite\" aria-atomic=\"true\"><\/p> <ul><\/ul>\n<\/div>\n<form action=\"\/wp-json\/wp\/v2\/pages\/561#wpcf7-f860-o1\" method=\"post\" class=\"wpcf7-form init\" aria-label=\"Contact form\" novalidate=\"novalidate\" data-status=\"init\">\n<label class=\"ebd_input\"><input type=\"hidden\" name=\"ebd_downloads[]\" value=\"588|Top 4 Verilog and SystemVerilog papers\"> <\/label><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"title|Top 4 Verilog and SystemVerilog papers\"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"checked|no\"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"hide_form|yes\"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"radio|no\"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"from_name| \"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"file_thumbnail|no\"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"item_id|2\"><input type=\"hidden\" class=\"ebd_setting\" name=\"ebd_settings[]\" value=\"form_id|wpcf7-f860-o1\"><div style=\"display: none;\">\n<input type=\"hidden\" name=\"_wpcf7\" value=\"860\">\n<input type=\"hidden\" name=\"_wpcf7_version\" value=\"5.7.6\">\n<input type=\"hidden\" name=\"_wpcf7_locale\" value=\"en_US\">\n<input type=\"hidden\" name=\"_wpcf7_unit_tag\" value=\"wpcf7-f860-o1\">\n<input type=\"hidden\" name=\"_wpcf7_container_post\" value=\"0\">\n<input type=\"hidden\" name=\"_wpcf7_posted_data_hash\" value=\"\">\n<input type=\"hidden\" name=\"_wpcf7_recaptcha_response\" value=\"\">\n<\/div>\n<p><label> Your Name (required)<br>\n<span class=\"wpcf7-form-control-wrap\" data-name=\"your-name\"><input size=\"40\" class=\"wpcf7-form-control wpcf7-text wpcf7-validates-as-required\" aria-required=\"true\" aria-invalid=\"false\" value=\"\" type=\"text\" name=\"your-name\"><\/span> <\/label>\n<\/p>\n<p><label> Your Email (required)<br>\n<span class=\"wpcf7-form-control-wrap\" data-name=\"your-email\"><input size=\"40\" class=\"wpcf7-form-control wpcf7-text wpcf7-email wpcf7-validates-as-required wpcf7-validates-as-email\" aria-required=\"true\" aria-invalid=\"false\" value=\"\" type=\"email\" name=\"your-email\"><\/span> <\/label>\n<\/p>\n<p>Answer <span class=\"wpcf7-form-control-wrap\" data-name=\"random-math-quiz\"><label><span class=\"wpcf7-quiz-label\">1+9<\/span> <input size=\"40\" class=\"wpcf7-form-control wpcf7-quiz\" autocomplete=\"off\" aria-required=\"true\" aria-invalid=\"false\" type=\"text\" name=\"random-math-quiz\"><\/label><input type=\"hidden\" name=\"_wpcf7_quiz_answer_random-math-quiz\" value=\"e55fe3da199c3789ce218c9829211b20\"><\/span>\n<\/p>\n<p><input class=\"wpcf7-form-control has-spinner wpcf7-submit\" type=\"submit\" value=\"Send me the papers!\">\n<\/p>\n<p style=\"display: none !important;\" class=\"akismet-fields-container\" data-prefix=\"_wpcf7_ak_\"><label>&Delta;<textarea name=\"_wpcf7_ak_hp_textarea\" cols=\"45\" rows=\"8\" maxlength=\"100\"><\/textarea><\/label><input type=\"hidden\" id=\"ak_js_1\" name=\"_wpcf7_ak_js\" value=\"89\"><script>document.getElementById( \"ak_js_1\" ).setAttribute( \"value\", ( new Date() ).getTime() );<\/script><\/p>\n<div class=\"wpcf7-response-output\" aria-hidden=\"true\"><\/div>\n<script> var wpcf7f860o1selectors = \"div#wpcf7-f860-o1 > form > .ebd_input > input\";\n        \n        jQuery( wpcf7f860o1selectors ).on( \"click\", function () {\n            var wpcf7f860o1n = jQuery( wpcf7f860o1selectors+\":checked\" ).length;\n            \n            if(wpcf7f860o1n > 0) jQuery(\"div#wpcf7-f860-o1 form \").children().not('.ebd_input').not('.wpcf7-response-output').not('script').show();\n            else jQuery(\"div#wpcf7-f860-o1 form \").children().not('.ebd_input').not('.wpcf7-response-output').not('script').hide();\n        } );    jQuery('.wpcf7-response-output').hide();\n<\/script>\n<\/form>\n<\/div>\n\n\n\n\n<p><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Get the top 4 Verilog and SystemVerilog papers that shaped how I code RTL today! Surprising fact: only 1 paper is about state machine coding<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"jetpack_post_was_ever_published":false,"footnotes":""},"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v22.6 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>Resources - Verilog Pro<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.verilogpro.com\/resources\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Resources - Verilog Pro\" \/>\n<meta property=\"og:description\" content=\"Get the top 4 Verilog and SystemVerilog papers that shaped how I code RTL today! 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