{"id":525,"date":"2017-04-15T11:49:52","date_gmt":"2017-04-15T18:49:52","guid":{"rendered":"http:\/\/www.verilogpro.com\/?page_id=525"},"modified":"2017-04-15T11:49:52","modified_gmt":"2017-04-15T18:49:52","slug":"systemverilog","status":"publish","type":"page","link":"https:\/\/www.verilogpro.com\/systemverilog\/","title":{"rendered":"SystemVerilog Category Posts"},"content":{"rendered":"<p>A listing of posts under the SystemVerilog category.<\/p>\n<h2>SystemVerilog<\/h2>\n<ul class=\"display-posts-listing\"><li class=\"listing-item\"><a class=\"title\" href=\"https:\/\/www.verilogpro.com\/systemverilog-arrays-synthesizable\/\">SystemVerilog Arrays, Flexible and Synthesizable<\/a><\/li><li class=\"listing-item\"><a class=\"title\" href=\"https:\/\/www.verilogpro.com\/verilog-reg-verilog-wire-systemverilog-logic\/\">Verilog reg, Verilog wire, SystemVerilog logic. What&#8217;s the difference?<\/a><\/li><li class=\"listing-item\"><a class=\"title\" href=\"https:\/\/www.verilogpro.com\/systemverilog-structures-unions-design\/\">SystemVerilog Struct and Union &#8211; for Designers too<\/a><\/li><li class=\"listing-item\"><a class=\"title\" href=\"https:\/\/www.verilogpro.com\/asynchronous-fifo-design\/\">Dual-Clock Asynchronous FIFO in SystemVerilog<\/a><\/li><li class=\"listing-item\"><a class=\"title\" href=\"https:\/\/www.verilogpro.com\/systemverilog-one-hot-state-machine\/\">One-hot State Machine in SystemVerilog &#8211; Reverse Case Statement<\/a><\/li><li class=\"listing-item\"><a class=\"title\" href=\"https:\/\/www.verilogpro.com\/systemverilog-always_comb-always_ff\/\">SystemVerilog always_comb, always_ff. New and Improved.<\/a><\/li><li class=\"listing-item\"><a class=\"title\" href=\"https:\/\/www.verilogpro.com\/systemverilog-unique-priority\/\">SystemVerilog Unique And Priority &#8211; How Do I Use Them?<\/a><\/li><li class=\"listing-item\"><a class=\"title\" href=\"https:\/\/www.verilogpro.com\/x-propagation-with-vcs-xprop\/\">SystemVerilog and Verilog X Optimism &#8211; Hardware-like X Propagation with Xprop<\/a><\/li><li class=\"listing-item\"><a class=\"title\" href=\"https:\/\/www.verilogpro.com\/systemverilog-verilog-x-optimism-pessimism\/\">SystemVerilog and Verilog X Optimism &#8211; What About X Pessimism?<\/a><\/li><li class=\"listing-item\"><a class=\"title\" href=\"https:\/\/www.verilogpro.com\/systemverilog-verilog-x-optimism\/\">SystemVerilog and Verilog X Optimism &#8211; You May Not Be Simulating What You Think<\/a><\/li><\/ul>\n","protected":false},"excerpt":{"rendered":"<p>A listing of posts under the SystemVerilog category. SystemVerilog<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"jetpack_post_was_ever_published":false,"footnotes":""},"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v22.6 - https:\/\/yoast.com\/wordpress\/plugins\/seo\/ -->\n<title>SystemVerilog Category Posts - Verilog Pro<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.verilogpro.com\/systemverilog\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"SystemVerilog Category Posts - Verilog Pro\" \/>\n<meta property=\"og:description\" content=\"A listing of posts under the SystemVerilog category. SystemVerilog\" \/>\n<meta property=\"og:url\" content=\"https:\/\/www.verilogpro.com\/systemverilog\/\" \/>\n<meta property=\"og:site_name\" content=\"Verilog Pro\" \/>\n<meta property=\"og:image\" content=\"http:\/\/www.verilogpro.com\/wp-content\/uploads\/2015\/09\/VLSIDesign-thumbnail.png\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:site\" content=\"@jasonkky\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":\"WebPage\",\"@id\":\"https:\/\/www.verilogpro.com\/systemverilog\/\",\"url\":\"https:\/\/www.verilogpro.com\/systemverilog\/\",\"name\":\"SystemVerilog Category Posts - Verilog Pro\",\"isPartOf\":{\"@id\":\"https:\/\/www.verilogpro.com\/#website\"},\"datePublished\":\"2017-04-15T18:49:52+00:00\",\"dateModified\":\"2017-04-15T18:49:52+00:00\",\"breadcrumb\":{\"@id\":\"https:\/\/www.verilogpro.com\/systemverilog\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/www.verilogpro.com\/systemverilog\/\"]}]},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/www.verilogpro.com\/systemverilog\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/www.verilogpro.com\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"SystemVerilog Category Posts\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/www.verilogpro.com\/#website\",\"url\":\"https:\/\/www.verilogpro.com\/\",\"name\":\"Verilog Pro\",\"description\":\"Verilog and Systemverilog Resources for Design and Verification\",\"publisher\":{\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/www.verilogpro.com\/?s={search_term_string}\"},\"query-input\":\"required name=search_term_string\"}],\"inLanguage\":\"en-US\"},{\"@type\":[\"Person\",\"Organization\"],\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af\",\"name\":\"Jason Yu\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/\",\"url\":\"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g\",\"contentUrl\":\"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g\",\"caption\":\"Jason Yu\"},\"logo\":{\"@id\":\"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/\"},\"description\":\"Jason has 14 years' experience in the semiconductor industry, designing and verifying Solid State Drive controller SoC. His areas of work include microarchitecture and RTL design, dynamic and formal verification using UVM and Cadence JasperGold, and full-chip low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in any way.\",\"sameAs\":[\"http:\/\/www.verilogpro.com\",\"https:\/\/ca.linkedin.com\/in\/jasonkky\",\"https:\/\/x.com\/jasonkky\"]}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"SystemVerilog Category Posts - Verilog Pro","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/www.verilogpro.com\/systemverilog\/","og_locale":"en_US","og_type":"article","og_title":"SystemVerilog Category Posts - Verilog Pro","og_description":"A listing of posts under the SystemVerilog category. SystemVerilog","og_url":"https:\/\/www.verilogpro.com\/systemverilog\/","og_site_name":"Verilog Pro","og_image":[{"url":"http:\/\/www.verilogpro.com\/wp-content\/uploads\/2015\/09\/VLSIDesign-thumbnail.png"}],"twitter_card":"summary_large_image","twitter_site":"@jasonkky","schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":"WebPage","@id":"https:\/\/www.verilogpro.com\/systemverilog\/","url":"https:\/\/www.verilogpro.com\/systemverilog\/","name":"SystemVerilog Category Posts - Verilog Pro","isPartOf":{"@id":"https:\/\/www.verilogpro.com\/#website"},"datePublished":"2017-04-15T18:49:52+00:00","dateModified":"2017-04-15T18:49:52+00:00","breadcrumb":{"@id":"https:\/\/www.verilogpro.com\/systemverilog\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/www.verilogpro.com\/systemverilog\/"]}]},{"@type":"BreadcrumbList","@id":"https:\/\/www.verilogpro.com\/systemverilog\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/www.verilogpro.com\/"},{"@type":"ListItem","position":2,"name":"SystemVerilog Category Posts"}]},{"@type":"WebSite","@id":"https:\/\/www.verilogpro.com\/#website","url":"https:\/\/www.verilogpro.com\/","name":"Verilog Pro","description":"Verilog and Systemverilog Resources for Design and Verification","publisher":{"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/www.verilogpro.com\/?s={search_term_string}"},"query-input":"required name=search_term_string"}],"inLanguage":"en-US"},{"@type":["Person","Organization"],"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/b1a5fb728f2c8b49eae25c635bdac5af","name":"Jason Yu","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/","url":"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/a40eb502eb5e595b80498d3126bb55b5?s=96&d=mm&r=g","caption":"Jason Yu"},"logo":{"@id":"https:\/\/www.verilogpro.com\/#\/schema\/person\/image\/"},"description":"Jason has 14 years' experience in the semiconductor industry, designing and verifying Solid State Drive controller SoC. His areas of work include microarchitecture and RTL design, dynamic and formal verification using UVM and Cadence JasperGold, and full-chip low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in any way.","sameAs":["http:\/\/www.verilogpro.com","https:\/\/ca.linkedin.com\/in\/jasonkky","https:\/\/x.com\/jasonkky"]}]}},"jetpack_sharing_enabled":true,"jetpack_shortlink":"https:\/\/wp.me\/P6Du8T-8t","jetpack-related-posts":[],"_links":{"self":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/pages\/525"}],"collection":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/comments?post=525"}],"version-history":[{"count":1,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/pages\/525\/revisions"}],"predecessor-version":[{"id":526,"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/pages\/525\/revisions\/526"}],"wp:attachment":[{"href":"https:\/\/www.verilogpro.com\/wp-json\/wp\/v2\/media?parent=525"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}