Comments on: Verilog Module for Design and Testbench https://www.verilogpro.com/verilog-module-for-design-and-testbench/ Verilog and Systemverilog Resources for Design and Verification Thu, 29 Sep 2022 08:01:35 +0000 hourly 1 https://wordpress.org/?v=6.5.3 By: Jason Yu https://www.verilogpro.com/verilog-module-for-design-and-testbench/#comment-7833 Thu, 29 Sep 2022 08:01:35 +0000 https://www.verilogpro.com/?p=784#comment-7833 In reply to Sanabhi.

Oops you’re right, a typo. I’ve fixed it now. Thanks!

]]> By: Sanabhi https://www.verilogpro.com/verilog-module-for-design-and-testbench/#comment-6410 Thu, 07 Jul 2022 08:07:52 +0000 https://www.verilogpro.com/?p=784#comment-6410 Hi,
This is going to throw an error as the module name is not mentioned after the module keyword.
module #(
parameter WIDTH = 1
) my_module (
It should be
module my_module #(
parameter WIDTH = 1
) (

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