Yes it is certainly synthesizable and can be implemented in FPGA.

Thanks for spotting the typo!

module for_loop_synthesis (i_Clock);
input i_Clock;
integer ii=0;
reg [3:0] r_Shift_With_For = 4’h1;
reg [3:0] r_Shift_Regular = 4’h1;

// Performs a shift left using a for loop
always @(posedge i_Clock)
begin
for(ii=0; ii<3; ii=ii+1)
r_Shift_With_For[ii+1] <= r_Shift_With_For[ii];
end

// Performs a shift left using regular statements
always @(posedge i_Clock)
begin
r_Shift_Regular[1] <= r_Shift_Regular[0];
r_Shift_Regular[2] <= r_Shift_Regular[1];
r_Shift_Regular[3] <= r_Shift_Regular[2];
end
endmodule

module for_loop_synthesis_tb (); // Testbench
reg r_Clock = 1'b0;
// Instantiate the Unit Under Test (UUT)
for_loop_synthesis UUT (.i_Clock(r_Clock));
always
#10 r_Clock = !r_Clock;
endmodule

module gray2bin
#(parameter SIZE = 8)
(
input [SIZE-1:0] gray,
output [SIZE-1:0] bin
);

generate
genvar gi;
// generate and endgenerate is optional
// generate (optional)
for (gi=0; gi<SIZE; gi=gi+1) begin : genbit
assign bin[gi] = ^gray[SIZE-1:gi];
end
// endgenerate (optional)
endgenerate
endmodule

module gray2bin_tb(); //Testbench
reg [15:0] in,out;

gray2bin #(16) DUT ( .gray(in), .bin(out) );

integer jj=0;

initial begin

for(jj=0;jj<16;jj=jj+1) begin
in=jj;
#5;
end
end

endmodule

i have corrected all of them for you

thank you for making this cheers

Yes you can also wrap always and assign statements in a generate.