Comments on: Verilog twins: case, casez, casex. Which Should I Use? https://www.verilogpro.com/verilog-case-casez-casex/ Verilog and Systemverilog Resources for Design and Verification Mon, 27 Jun 2022 07:43:12 +0000 hourly 1 https://wordpress.org/?v=6.4.4 By: Joon https://www.verilogpro.com/verilog-case-casez-casex/#comment-2742 Tue, 30 Mar 2021 09:38:51 +0000 http://www.verilogpro.com/?p=96#comment-2742 You are not posting anymore at the moment?

It helped me a lot with my understanding in Verilog and my projects.

Thank you I appreciate.

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By: shlomo eilon https://www.verilogpro.com/verilog-case-casez-casex/#comment-2194 Mon, 18 May 2020 12:46:04 +0000 http://www.verilogpro.com/?p=96#comment-2194 Hello
In VHDL there is an case option as the following:

signal counter : integer
case counter
when 1 to 10 => data_s

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By: Jason Yu https://www.verilogpro.com/verilog-case-casez-casex/#comment-1776 Thu, 01 Aug 2019 21:56:50 +0000 http://www.verilogpro.com/?p=96#comment-1776 In reply to Arushi.

Hi Arushi. I’m not sure I wrote exactly that casez and casex use === for comparing. What I meant was casez and casex will both do 4-state matching in simulation (similar to behaviour of ===), as opposed to 2-state matching (similar to behaviour of ==). casez and casex are synthesizable, with the caveats mentioned in this article.

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By: Arushi https://www.verilogpro.com/verilog-case-casez-casex/#comment-1687 Thu, 13 Jun 2019 18:58:42 +0000 http://www.verilogpro.com/?p=96#comment-1687 If casez and casex use === for comparing case expressions and case items, how are they synthesizable (since === to compare X or Z isn’t synthesizable)?

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By: Jason Yu https://www.verilogpro.com/verilog-case-casez-casex/#comment-1571 Tue, 09 Apr 2019 06:27:10 +0000 http://www.verilogpro.com/?p=96#comment-1571 In reply to Yogesh.

Hi Yogesh. What casex and casez synthesizes to depends on whether any of the signals in the case expression or case items are x or z (or case item has a wildcard ?). If none of the signals behave that way, then casex and casez behave and synthesize exactly like case. But if a signal does have the value of x or z (or case item has a wildcard ?), then casex and casez will behave and synthesize differently.

To your question of whether HW can detect X or Z. Keep in mind X is not a real value that exists in synthesized HW. X is a simulation only concept, to mean contention or uninitialized signal in simulation. The danger with using casex is a signal with X will take one deterministic code path in simulation, but in synthesized HW it is going to be unpredictably 1 or 0, and will cause HW to potentially execute a different code path than in simulation, perhaps resulting in unexpected behaviour. Similar idea applies to Z, which means unconnected signal in simulation. But a synthesis tool may tie an unconnected signal to an actual value during synthesis, causing potentially another difference in behaviour between simulation and actual HW.

Personally I avoid casex, and I only use casez if I specifically need to use the wildcard ? in a case item or case expression to simplify coding. If I don’t need any wildcard behaviour I stick with plain case.

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By: Yogesh https://www.verilogpro.com/verilog-case-casez-casex/#comment-1546 Sun, 31 Mar 2019 15:17:15 +0000 http://www.verilogpro.com/?p=96#comment-1546 Hi Jason,

Enjoyed reading your post.

I have an quick question on how case, casex and casez will be inferred in terms of gates? Will be the synthesized logic look same in all three flavors?

Can H/W detect if the signal is “X” or “Z” ?

Thanks

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By: Jason Yu https://www.verilogpro.com/verilog-case-casez-casex/#comment-1148 Sat, 29 Sep 2018 05:49:18 +0000 http://www.verilogpro.com/?p=96#comment-1148 In reply to Y.V.V.Nagendra.

Actually, they are synthesizable. However, they are prone to situations where the synthesis result may not match your simulation result. See this paper RTL Coding Styles that Yield Simulation and Synthesis Mismatches. So I would try to avoid using them in synthesizable code.

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By: Y.V.V.Nagendra https://www.verilogpro.com/verilog-case-casez-casex/#comment-1133 Sat, 22 Sep 2018 06:16:02 +0000 http://www.verilogpro.com/?p=96#comment-1133 Casez & casex are not synthesizeable, are they?

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By: Jason Yu https://www.verilogpro.com/verilog-case-casez-casex/#comment-898 Sat, 05 May 2018 16:38:50 +0000 http://www.verilogpro.com/?p=96#comment-898 In reply to Hetal.

Hi Hetal. Like described in the article, you must be very careful when using casex because X’s that you may not expect or know about, from a signal in the case item or case statement, can potentially cause an unwanted case code path to be executed and the logic to not behave as expected. X’s are relatively common in simulations—flip flops without reset, SRAMs that have not been written to, selecting an invalid index of a vector—can all cause X’s to appear on a signal. When these signals go into a casex statement, the casex may select a code path that you did not expect (unless you really know what you’re doing). So it’s safer to avoid the potential problem in the first place.

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By: Hetal https://www.verilogpro.com/verilog-case-casez-casex/#comment-897 Sat, 05 May 2018 13:12:43 +0000 http://www.verilogpro.com/?p=96#comment-897 Casex should never be used in Synthesizable code – Why?

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