Hi Jason. Thank you for replying back. I’m sorry that the question is not very clear. Yes, I wanted to ask how to write data from a 1D array into consecutive locations of a memory in verilog.

Thank you…

Hi Gautham. Sorry I don’t fully understand your question. A 1D array has multiple elements. How can you write that into one location of a memory? Or you mean you want to write it to multiple consecutive locations of the memory?

Thanks in Advance…

Hi Chetana. If you want to instantiate a module multiple times in an array, you need to use a generate loop. See my article Verilog Generate Configurable Designs.

Thanks In Advance

Hi. See an example I created on edaplayground here.

I have a doubt regarding 2D arrays in Verilog. Suppose I want a design which take two 2D arrays as inputs and gives an output as 2D array. When I tried to declare the input output ports as 2D arrays, it did not work at all.
I request you to kindly suggest me the way i can do my above said task in verilog.

Thanks in Advance…..

Hi Stefan. I think internally depending on which way you define the array, it does potentially affect the location of where the data is placed (e.g. where array1[0] is located). But that will be transparent you when coding RTL as long as you use the indices consistently. SystemVerilog actually allows you to define an array with just array1[SIZE], which is the same as array1[0:SIZE-1].