Yep! You are right Yuchao. I got the same doubt and in-fact I checked the original paper that Jason has referred “https://sutherland-hdl.com/papers/2013-DVCon_In-love-with-my-X_paper.pdf”. The published paper has this typo too 🙂

Great post as always!
There’s a typo in this code. In the assert statement, is should be (^cond !== 1’bx).

`define assert_condition (cond) \
assert (^cond === 1’bx) \
else $error(“%m, ifcond = X”)

Hi Shrikant. That’s an interesting question. Yes clk changing 0->X would cause this block to execute, at which point clk_1 will be inverted. Just thinking about it I don’t see how VCS will know clk=X actually needs to propagate to clk_1 because neither of the “if” nor “else” statement can cause an X to go on to clk_1. So my guess is no, but it would be good to confirm with a Synopsys AE because I don’t know exactly how the xprop algorithm works internally.

always @(posedge clk)
if(rst)
clk_1=0;
else
clk_1=~clk_1;

Suppose simulation is going fine, clk_1 is toggling properly based on posedge clk, but if after some time clk is changing 0-x , it will treat as posedge and once again clk_1 will toggling and now clk is remains ‘x’ for some time. so my question is if clk-x for some time it will also change the value of clk_1 to x ??

Thank you in advance.

Hi Kanta. I’m afraid I have not seen that error message… I would recommend contacting your local Synopsys AE to see if they can help you.