Comments on: SystemVerilog Arrays, Flexible and Synthesizable https://www.verilogpro.com/systemverilog-arrays-synthesizable/ Verilog and Systemverilog Resources for Design and Verification Sun, 26 Jun 2022 07:08:33 +0000 hourly 1 https://wordpress.org/?v=6.4.4 By: Jason Yu https://www.verilogpro.com/systemverilog-arrays-synthesizable/#comment-6311 Tue, 21 Jun 2022 15:00:22 +0000 http://www.verilogpro.com/?p=607#comment-6311 In reply to Veli.

Hi Veli. I think that should be synthesizable. I have written similar code where the LHS is a dynamic index to an array. I have not additionally used a fixed width slice, but I think since the width is a fixed parameter, it shouldn’t be a problem. A dynamic index and a dynamic width, I think would be a problem.

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By: Veli https://www.verilogpro.com/systemverilog-arrays-synthesizable/#comment-6290 Fri, 17 Jun 2022 09:21:57 +0000 http://www.verilogpro.com/?p=607#comment-6290 Is accessing to array slices with dynamic indexing but fixed width synthesizable?
For example:

// input_byte is a 8 bit logic input
// input_index is 3 bit logic input
localparam int unsigned FIXED_WIDTH = 8;
logic[63:0] data_array;
data_array[input_index *FIXED_WIDTH +: FIXED_WIDTH] <= input_byte;

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By: Jason Yu https://www.verilogpro.com/systemverilog-arrays-synthesizable/#comment-5371 Sun, 20 Mar 2022 16:21:52 +0000 http://www.verilogpro.com/?p=607#comment-5371 In reply to Yunsung Mo.

Hi Yunsung. I just ran a test to prove it to myself. You’re right! Thanks for correcting this major mistake!

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By: Yunsung Mo https://www.verilogpro.com/systemverilog-arrays-synthesizable/#comment-4966 Fri, 04 Feb 2022 08:52:02 +0000 http://www.verilogpro.com/?p=607#comment-4966 Always thanks to your post. Again, I hope to ask clarify below comment.
///////////////////////////////////////////////////////////////////////////
bit [3:0] [7:0] joe [0:9] // 10 elements of 4 8-bit bytes
// (each element packed into 32 bits)
typedef bit [4:0] bsix; // multiple packed dimensions with typedef
bsix [9:0] v5; // equivalent to bit[4:0][9:0] v5
typedef bsix mem_type [0:3]; // array of four unpacked ‘bsix’ elements
mem_type ba [0:7]; // array of eight unpacked ‘mem_type’ elements
// equivalent to bit[4:0] ba [0:3][0:7] – thanks Dennis!
///////////////////////////////////////////////////////////////////////////
Considering its semantic, I think it needs to be fixed as below.
In my previous experience, I was also confused for that.
1. equivalent to bit[4:0][9:0] v5 => equivalent to bit[9:0][4:0] v5
2. equivalent to bit[4:0] ba [0:3][0:7] => equivalent to bit[4:0] ba [0:7][0:3]

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By: Jason Yu https://www.verilogpro.com/systemverilog-arrays-synthesizable/#comment-2976 Fri, 18 Jun 2021 16:38:21 +0000 http://www.verilogpro.com/?p=607#comment-2976 In reply to Wai Ho Wu.

Haha hard to find time with work and a kid. Wish I had time to write more.

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By: Jason Yu https://www.verilogpro.com/systemverilog-arrays-synthesizable/#comment-1771 Wed, 31 Jul 2019 23:21:01 +0000 http://www.verilogpro.com/?p=607#comment-1771 In reply to Venkat M.

Hi Venkat. The array definition makes extracting one dimension easier than the other, so you should be careful about how you define the array. To accomplish what you want to do, you can write a loop to extract each element that you need and assign that element to a new 256-entry single dimensional array.

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By: Jason Yu https://www.verilogpro.com/systemverilog-arrays-synthesizable/#comment-1770 Wed, 31 Jul 2019 23:18:25 +0000 http://www.verilogpro.com/?p=607#comment-1770 In reply to Agnes.

Hi Agnes. If you create an unpacked struct (typedef struct, without the packed keyword), then you can have an unpacked array like the wr_pending_fifo_mem in the structure. However, Design Compiler will not synthesize an unpacked struct. What are you trying to achieve? Putting a FIFO into a struct seems to be a bit of a strange construct.

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By: Agnes https://www.verilogpro.com/systemverilog-arrays-synthesizable/#comment-1765 Tue, 30 Jul 2019 20:55:26 +0000 http://www.verilogpro.com/?p=607#comment-1765 Hi Jason,

Can I include an unpacked array in a struct or an interface? For example, I like to pass an FIFO and some other info of a module to another to snooping. can I have a struct like this:
typedef struct packed {
logic [5:0] dev_sel;
logic [31:0] wr_pending_fifo_dv;
logic [31:0] wr_pending_fifo_mem [128];
} dev_wr_fifo_s;

Would an interface have the same elements?

Thanks
Agnes

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By: Venkat M https://www.verilogpro.com/systemverilog-arrays-synthesizable/#comment-1761 Fri, 26 Jul 2019 15:03:16 +0000 http://www.verilogpro.com/?p=607#comment-1761 Hi want to extract only columns in packed 2-D array, for eg
logic [255:0][299:0] array1
has 256 rows each having 300 bits ; if I wanted to extract 1st column through array slicing operation how do I do it?
Like array1[0] gives first row array1[1] gives second row etc ;
Thanks a lot

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By: Babun Chandra Pal https://www.verilogpro.com/systemverilog-arrays-synthesizable/#comment-1470 Mon, 25 Feb 2019 07:51:03 +0000 http://www.verilogpro.com/?p=607#comment-1470 In reply to Jason Yu.

Thank you Jason for your venerated inputs.

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