Thanks for your thoughtful comment. Looking at the paper again it seems I did modify the circuit slightly on the receiver side. You’re absolutely right. I’m more used to a feed forward kind of design, so my design goal was to present data on the destination domain together with asserting dest_valid. With that, my assumption was the destination logic would not assert dest_ack until it has captured dest_data_out signal. But I see how the original circuit could have potentially saved an extra capture flop to capture dest_data_out.

Hi. What simulator are you running the code with? I checked the code with VCS on http://www.edaplayground.com . Can you try running it there?