Yes that will work too. But for a real life design you should separate the test bench from the design so the design files can be taken through the complete design flow including synthesis and physical design.

Hi. Yes each of the pointers are multi-bit, in parallel. Therefore each of the bits require a 2-flop synchronizer.

Hi Dong. I simulated my code at edaplayground.com using Synopsys VCS.

Hi Max. I realized there is an important detail I missed/assumed in the article. Besides coding the RTL design correctly, there also needs to be a timing constraint placed on the signals of the gray code. The timing constraint has to say that each of the bits of the gray code, must be sent from the fast to slow clock, within 1 cycle of the fast clock. This is a timing constraint on the physical wire, to constrain the flight time of the signal on the wire. With this constraint, it will ensure that the recipient flip flops, on the slow clock, will see the values changing 1 bit at a time (at the rate of the fast clock). Therefore at any point in time when the slow clock ticks, there can only have been 1 bit transition on the gray code signals.

But if one or more values are skipped, then back-to-back values seen by the (slow) receiver can differ by more than one bit, despite the use of gray code. Is this not a problem?

Oops, typo in the comments.