SystemVerilog always_comb, always_ff. New and Improved.
Verilog engineers will be familiar with using Verilog always to code recurring procedures like sequential logic (if not, refer to my article Verilog Always Block for RTL Modeling), and most will have used always @(*) to code combinational logic. SystemVerilog defines four forms of always procedures: always, always_comb, always_ff, always_latch. What do the three new … Read more