Comments for Verilog Pro

Comment on SystemVerilog and Verilog X Optimism – Hardware-like X Propagation with Xprop by Jason Yu

Jason Yu — Fri, 23 Dec 2022 01:45:16 +0000

In reply to Ferdous.

Not that I know of… In the past I had spent many hours hunting down exactly where the X originated from.

Comment on SystemVerilog and Verilog X Optimism – Hardware-like X Propagation with Xprop by Ferdous

Ferdous — Thu, 22 Dec 2022 09:03:24 +0000

Is it possible to generate report that tell you where the x originated from?

Comment on Dual-Clock Asynchronous FIFO in SystemVerilog by Jason Yu

Jason Yu — Sun, 16 Oct 2022 20:01:36 +0000

In reply to Hari. Yes that will work too. But for a real life design you should separate the test bench from the design so the design files can be taken through the complete design flow including synthesis and physical design.

Comment on Dual-Clock Asynchronous FIFO in SystemVerilog by Hari

Hari — Sun, 16 Oct 2022 17:57:07 +0000

Hey Jason ,
can we implement the same code with only one testbench and design file.

Comment on Verilog Module for Design and Testbench by Jason Yu

Jason Yu — Thu, 29 Sep 2022 08:01:35 +0000

In reply to Sanabhi. Oops you're right, a typo. I've fixed it now. Thanks!

Comment on SystemVerilog Struct and Union – for Designers too by Jason Yu

Jason Yu — Thu, 29 Sep 2022 07:58:51 +0000

In reply to craig. Ah yes, missed the slashes before the comments. Thanks!

Comment on SystemVerilog Struct and Union – for Designers too by craig

craig — Wed, 28 Sep 2022 18:21:25 +0000

Hi Jason,

I noticed another typo in your second code example:
my_opcode_struct_t opcode_s; “fields view” to the struct
Should be:
my_opcode_struct_t opcode_s; // “fields view” to the struct

Keep the helpful articles coming.

Comment on Verilog Module for Design and Testbench by Sanabhi

Sanabhi — Thu, 07 Jul 2022 08:07:52 +0000

Hi,
This is going to throw an error as the module name is not mentioned after the module keyword.
module #(
parameter WIDTH = 1
) my_module (
It should be
module my_module #(
parameter WIDTH = 1
) (

Comment on SystemVerilog Arrays, Flexible and Synthesizable by Jason Yu

Jason Yu — Tue, 21 Jun 2022 15:00:22 +0000

In reply to Veli. Hi Veli. I think that should be synthesizable. I have written similar code where the LHS is a dynamic index to an array. I have not additionally used a fixed width slice, but I think since the width is a fixed parameter, it shouldn't be a problem. A dynamic index and a dynamic width, I think would be a problem.

Comment on SystemVerilog always_comb, always_ff. New and Improved. by Jason Yu

Jason Yu — Sun, 19 Jun 2022 00:21:02 +0000

In reply to Alexis. Hi Alexis. Yes you're absolutely correct. I was trying to illustrate the difference between two different code snippets. I was intending the two snippets to be considered separately, not together as one module/file. I've tried to make that more clear by separating the text into two separate snippets.