A listing of all posts by category.
Verilog
- Verilog Module for Design and Testbench
- Verilog Always Block for RTL Modeling
- Verilog Generate Configurable RTL Designs
- Verilog Arrays Plain and Simple
- Verilog reg, Verilog wire, SystemVerilog logic. What’s the difference?
- Verilog twins: case, casez, casex. Which Should I Use?
- SystemVerilog and Verilog X Optimism – Hardware-like X Propagation with Xprop
- SystemVerilog and Verilog X Optimism – What About X Pessimism?
- SystemVerilog and Verilog X Optimism – You May Not Be Simulating What You Think
SystemVerilog
- SystemVerilog Arrays, Flexible and Synthesizable
- Verilog reg, Verilog wire, SystemVerilog logic. What’s the difference?
- SystemVerilog Struct and Union – for Designers too
- Dual-Clock Asynchronous FIFO in SystemVerilog
- One-hot State Machine in SystemVerilog – Reverse Case Statement
- SystemVerilog always_comb, always_ff. New and Improved.
- SystemVerilog Unique And Priority – How Do I Use Them?
- SystemVerilog and Verilog X Optimism – Hardware-like X Propagation with Xprop
- SystemVerilog and Verilog X Optimism – What About X Pessimism?
- SystemVerilog and Verilog X Optimism – You May Not Be Simulating What You Think
Design
- Verilog Module for Design and Testbench
- Verilog Always Block for RTL Modeling
- Verilog Generate Configurable RTL Designs
- SystemVerilog Struct and Union – for Designers too
- Clock Domain Crossing Design – Part 3
- Clock Domain Crossing Design – Part 2
- Clock Domain Crossing Design – 3 Part Series
- Dual-Clock Asynchronous FIFO in SystemVerilog